objective questions DSD HDL

 

multiple choice questions 

4) The Verilog is modelled for the ________ devices.

• A. condution
• B.electrical
• C.electronics
• D.All of the above

6) The _________ is the first version of the Verilog.

• A. IEEE standard 1364-1994
• B.IEEE standard 1364-2000
• C.IEEE standard 1364-1995
• D.IEEE standard 1364-1997

8) ________ provides multiple-valued logic with eight signal strength.

• A. C
• B.Verilog
• C.C++
• D.Java

9) _______ is a superset of Verilog.

• A. Verilog
• B.System Verilog
• C.VHDL
• D.System VHDL

11) _________ hardware description language is more flexible.

• A. C
• B.Java
• C.Verilog
• D.VHDL

20) ________ operator is used to trigger an event.

• A. @
• B.&
• C.$$
• D.==

21) In continuous assignment statement LHS can be _________.

• A. Vector net
• B.Scalar net Vector net
• C.Concatenation of both
• D.All of the above

22) ________ is used to introduce delays in a circuit.

• A. Flip-flops
• B.EXOR gate
• C.Inverter
• D.Buffer

23) Arrays are not allowed for _________.

• A. characters
• B.time
• C.real
• D.bool

24) @posedge means ________ .

• A. Transition from 0 to 1,x or z
• B.Transition from x to 1
• C.Transition from z to 1
• D.Transition from z to x

26) The wait statement is _________.

• A. edge sensitive
• B.level sensitive
• C.Both A and B
• D.None of the above

27) The possible values of the == operator are __________.

• A. 0
• B.1
• C.x
• D.All of the above

28) The default value for reg data type is ______.

• A. 0
• B.1
• C.x
• D.z

29) __________ is used to overwrite the value of a parameter during module instantiation.

• A. `ifdef
• B.`timescale
• C.`define
• D.`include

30) ______ defines special parameters in the specify block.

• A. specparam
• B.param
• C.defparam
• D.parameter

 

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