Parity Generators and Checkers in Verilog

 Parity Generators and Checkers in Verilog

    While transferring or storing binary data, some bit values may change because of a physical effect or an unpredicted disturbance. 

    To check whether such an undesired change has occurred or not, extra bits can be added to the data. This is called parity generation. 

Parity Generators:

In parity, generation is adding an extra bit to set the total number of bits in a binary data block as even or odd. 

The idea here is as follows. If a bit value changes from logic level 1 to 0 (or vice versa) by an undesired effect, the total number of even (or odd) bits will not satisfy the initial condition.

There are two options here.

 The first option is setting the total number of ones to be even. This is called even parity. 

The second option is setting the total number of ones to be odd. This is called odd parity.

example: consider three-bit data.

the three-bit data is represented by binary variables b0, b1, and b2. The generated even-parity bit is represented by binary variable pe.

Truth Table of Three-Bit Even-Parity Generator

The even-parity bit can be generated by the logic function 

                    pe = b0 ⊕ b1 ⊕ b2.

The even-parity generator can be composed of two XOR gates with two inputs

    Circuit diagram of three-bit even-parity generator

Verilog Description of Three-Bit Even-Parity Generator:

Parity Checkers:

After adding a parity bit, we can construct a combinational circuit to check whether an undesired change has occurred in the data during transmission or storage.

 To do so, we can use the same circuitry as in the parity generator with an additional parity bit. This is called parity checker

Parity checker circuitry can be constructed by logic function 

                            C =b0 ⊕ b1 ⊕ b2  ⊕ pe

Circuit diagram of three-bit even-parity checker

Verilog Description of Three-Bit Even-Parity Checker

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