Mid -1 important questions

 

 IMPORTANT QUESTION

1.     Write brief notes architecture of Xilinx Artix-7 FPGA          

2.    Explain test bench formation in Verilog?                                                      

3.     Compare the properties and peripherals of Basys3 & arty boards.

4.     Explain Data Types in Verilog? Write a Verilog code & test bench code to explain the Data Types in Verilog.

5.   Explain bitwise, concatenation, replication operators in Verilog with example

6.     Explain arithmetic operators in Verilog? Write a Verilog code & test bench code to explain the arithmetic operators in Verilog.

7.     Explain concatenation & replication operators? Write a Verilog code & test bench code to explain the concatenation & replication operators in Verilog.

8.     Explain logical, bitwise & reduction operators in Verilog? Write a Verilog code for each operator?

9.     Explain relational & equality operators in Verilog? Write a Verilog code for each operator?

10.     Explain shift operators in Verilog? Write a Verilog code for each operator?

11.     Explain conditional operators in Verilog? Write a Verilog code for each operator?

12.  Tabulate all the operators in Verilog with operator type, operator symbol, operation performed & no of operands (4 columns)?

13.  (Two’s complement calculator.) Design a combinational circuit with the following specifications. Input to the circuit is a three-bit unsigned number. Output of the circuit is two’s complement of input. Implement the designed combinational circuit either in Verilog.

14.  A combinational circuit is represented in the SOP form F(x, y, z) = Σ(0, 2, 4, 6).

             a. Describe this circuit in Verilog using dataflow modelling.

 b. Obtain the simplest form of this circuit.

15.  A combinational circuit is represented by logic function F(x, y, z) = x · z + x · y. Implement

this circuit using         a. an eight-to-one multiplexer.

b. four-to-one and two-to-one multiplexers.

c. two-to-one multiplexers.

16.  (Even/odd number detector.) Design an even/odd number detector with the following             specifications. Input to the system is a four-bit number. If the number is even, the first output will be logic level 1. Otherwise, the second output will be logic level 1.  Implement the designed combinational circuit either in Verilog.

17. Implement a four-bit full adder/subtractor. The user decides on operation type by a control input. When the control input is logic level 1, the subtraction will be done. When the control input is logic level 0, addition is done. Implement this device in Verilog.

18.  Design an eight-bit comparator for unsigned numbers. Implement this device in Verilog, Repeat for eight-bit signed numbers.

 

19.  Implement the two-to-four decoder in Verilog using

a. case keyword.                     b. if keyword. 

22.  (Even/odd number detector.) Design a combinational circuit to detect whether a given N-bit number is even or odd. Implement the designed circuit using arithmetic operations and conditional statements in Verilog

23.  Use the full adder block, to add two four-bit numbers. Implement this device in Verilog    

24.(Fire alarm system.) Design a fire alarm system with the following specifications. The system has an on/off switch. The system works only if the switch is on. There is a smoke detector giving the output in three bits. When the smoke density is maximum, the output of the sensor is seven in binary form. When there is no smoke detected, the output of the sensor is zero in the binary form. The alarm will be active if the output of the smoke detector exceeds four in the binary form. Implement the designed combinational circuit either in Verilog   

   

25.(Simple safety belt alarm system for cars.)

Design a simple safety belt alarm system for cars. Only the front seat safety belts are of focus. The alarm system works as follows. If the car engine has started, the passenger has seated, and the passenger has not plugged in the belt, then the alarm signal starts till the belt has been plugged in. The engine status (started or not) is provided by a digital signal. If the engine has started and operating, logic level 1 is fed. Otherwise, logic level 0 is fed. Pressure sensor attached to the driver and passenger seats provides a digital signal with logic level 1 when a mass produces pressure. Otherwise, the sensor provides logic level 0. The safety belt plug-in apparatus has a digital sensor such that when the belt is plugged in, it produces logic level 1. Otherwise, it produces logic level 0. Although an audio alarm signal is desirable, in this question we will use two LEDs to indicate the alarm. If the driver has seated, started the engine, and not plugged the belt, the alarm will turn on till the belt is plugged in. The same settings in the driver seat apply to the passenger seat. Please note that the two-seat alarms operate independently. Implement the designed combinational circuit either in Verilog or VHDL.          

26. DESIGN A HOME ALARM SYSTEM USING VERILOG HDL?

27. DESIGN A CAR PARK OCCUPIED SLOT COUNTING SYSTEM USING VERILOG HDL?  

28. DESIGN A DIGITALSAFE  SYSTEM USING VERILOG HDL?

           ***

Course Outcomes:

At the end of this course, the student will be able to

1.     Understand the architecture of FPGAs, tools used in modelling of digital design

2.     Analyze and design basic digital circuits with combinatorial and sequential logic circuits

using Verilog HDL.

3.     Model complex digital systems at several levels of abstractions.

4.     Design real-time applications such as vending machine and washing machines etc.