Home Alarm System (Using sequential circuits)
Using sequential circuits can improve the home alarm system. To do so, we can add password, buzzer, and LED blink modules to the system.
The modified system works as follows.
· Once the alarm is activated by pressing btnC on the Basys3 board, the rightmost seven-segment display digit shows character A. This indicates that the system is active.
· If one of the windows is opened, then the alarm LED turns on to indicate that alarm has turned on. Hence, the buzzer starts working.
· If the user enters the correct password, then the alarm is deactivated. Hence, the buzzer stops. If the door is opened, then the user has 20 seconds to enter the password. If the correct password is entered within this time slot, then the alarm turns off.
· Otherwise, the alarm LED turns on and buzzer starts working. Counting of 20 seconds is displayed on the two leftmost seven segment display digits of the Basys3 board.
Verilog Description of the Modified Home Alarm Module via Sequential Circuits (CODE-1)
Verilog description for the home alarm module has seven inputs.
· These are clk (main clock signal
· pass (eight-bit password)
· act (activation signal)
· door (door input)
· win1, win2, win3 (window inputs).
· Door and window inputs are at logic level 1 when they are open. Otherwise they are at logic level 0.
The module has five outputs. These are
· blinkled (warning LED during alarm countdown)
· alarmled (shows the alarm status)
· seg, an (seven-segment display ports)
· buzzer (the buzzer output).
****************************************************************************
(CODE-1):
module home_alarm2 (clk, pass, act,door,win1,win2,win3,blinkled, alarmled, seg,an,buzzer);
input clk;
input [7:0] pass;
input act, door, win1, win2, win3;
output reg blinkled=0, alarmled=0;
output [6:0] seg;
output [3:0] an;
output reg buzzer=1;
localparam AOFF=2'b00, AON=2'b01, PASSCHECK=2'b10, SOUND=2'b11;
reg [1:0] state=AOFF;
integer passcounter=0;
localparam secondtime=100000000; //1 second
reg [7:0] seconds=0;
parameter password=8'h55;
reg [3:0] active=4'b0000;
wire [3:0] thos,huns,tens,ones;
binarytoBCD_0 bin ({4'b0000,seconds},thos,huns,tens,ones);
sevenseg_driver_0 seg7 (clk,1'b0,tens,ones,4'b0000,active,seg,an);
always @ (posedge clk)
case(state)
AOFF:
if (act == 1) state <= AON;
AON:
if (door != 0) state <= PASSCHECK;
else if ((win1 | win2 | win3) != 0) state <= SOUND;
PASSCHECK:
if (passcounter == secondtime)
begin
seconds <= seconds + 1'b1;
blinkled <= ~blinkled;
passcounter <= 0;
end
else
if (pass == password) begin
blinkled <= 0;
seconds <= 0;
state <= AOFF;
end
else if (seconds == 8'b0001_0100)
begin
blinkled <= 0;
seconds <= 0;
state <= SOUND;
end
else passcounter <= passcounter + 1;
SOUND:
if (pass == password)
begin
alarmled <= 0;
state <= AOFF;
buzzer <= 1;
end
else begin
alarmled <= 1;
buzzer <= 0;
end
endcase
always @ (posedge clk)
case (state)
AOFF:
active <= 4'b0000;
AON:
active <= 4'b1010;
endcase
endmodule
************************************************************************
Working principles of the modified home alarm module:
The state machine has four states as AOFF, AON, PASSCHECK, and SOUND. When act goes to logic level 1, state changes from AOFF to AON.
· There are two options here. If one of the windows are opened, state machine directly goes to SOUND state which sounds the alarm.
· If the door is opened, state machine goes to PASSCHECK state.
· Here, the machine waits for 20 seconds for the user to enter password. The password is initially set to 55H in the hexadecimal form. If the entered password is correct, then the machine goes to AOFF state. Otherwise, the state machine goes to SOUND state which sounds the alarm.
· IP modules binarytoBCD_0 and sevenseg_driver_0 should be added to the project.
Seven-Segment Display Driver Module in Verilog for Four Digits (CODE-2)
The main purpose of this module is to drive the seven-segment display on the FPGA board. This display is a “common anode” type four-digit display. There are seven signals, named as seg, to drive four digits commonly, and four-digit enable signal, named an, to enable each digit. Since these are all common anode signals, they should be set to logic level 0 when they are active. Since four digits have common seg signals, an signal should be periodically changed at a rate faster than the human eye can catch.
In every step, seven-bits seg data will be fed to the selected digit.
We provide the Verilog description of the module
The module has six inputs as
· clk (main clock),
· clr (active-high reset),
· four four-bit digit inputs in1, in2, in3, in4.
Outputs of the module are seg and an.
The working principle of the seven-segment display driver module.
First, we need to divide input clock by 212 to drive segments.
If clr goes to logic level 1 at anytime, both seg and an go to logic level 0.
Then, all digits and segments are turned on and 8888 is seen on the display. Otherwise, a state machine starts. We have four states to indicate the position of digits from left to right.
Note that four-bit inputs have been converted into seven-bit seven-segment codes with the module decoder_7seg in (CODE-3)
The state machine starts in LEFT state where the decoded pattern is loaded to seg and the first digit from left is selected by loading 0111 to an.
Next, state turns to MIDLEFT. The same operation is done to drive the second digit from left. This continues in a loop for all four digits in the display.
**************************************************************
(CODE-2):
module sevenseg_driver(clk,clr,in1,in2,in3,in4,seg,an);
input clk, clr;
input [3:0] in1, in2, in3, in4;
output reg [6:0] seg;
output reg [3:0] an;
wire [6:0] seg1, seg2, seg3, seg4;
reg [12:0] segclk;
localparam LEFT = 2'b00, MIDLEFT = 2'b01, MIDRIGHT = 2'b10, RIGHT = 2'b11;
reg [1:0] state=LEFT;
decoder_7seg disp1(in1,seg1);
decoder_7seg disp2(in2,seg2);
decoder_7seg disp3(in3,seg3);
decoder_7seg disp4(in4,seg4);
always @ (posedge clk)
segclk <= segclk + 1'b1;
always @(posedge segclk[12] or posedge clr)
begin
if (clr == 1)
begin
seg <= 7'b0000000;
an <= 7'b0000;
state <= LEFT;
end
else begin
case(state)
LEFT:
begin
seg <= seg1;
an <= 4'b0111;
state <= MIDLEFT;
end
MIDLEFT:
begin
seg <= seg2;
an <= 4'b1011;
state <= MIDRIGHT;
end
MIDRIGHT:
begin
seg <= seg3;
an <= 4'b1101;
state <= RIGHT;
end
RIGHT:
begin
seg <= seg4;
an <= 4'b1110;
state <= LEFT;
end
endcase
end
end
endmodule
****************************************************************************
(CODE-3)
decoder_7seg Driver Module in Verilog:
module decoder_7seg(in1,out1);
input [3:0] in1;
output reg [6:0] out1;
always @ (in1)
case (in1)
4'b0000 : out1=7'b1000000; //0
4'b0001 : out1=7'b1111001; //1
4'b0010 : out1=7'b0100100; //2
4'b0011 : out1=7'b0110000; //3
4'b0100 : out1=7'b0011001; //4
4'b0101 : out1=7'b0010010; //5
4'b0110 : out1=7'b0000010; //6
4'b0111 : out1=7'b1111000; //7
4'b1000 : out1=7'b0000000; //8
4'b1001 : out1=7'b0010000; //9
4'b1010 : out1=7'b0001000; //A
4'b1011 : out1=7'b0000011; //B
4'b1100 : out1=7'b1000110; //C
4'b1101 : out1=7'b0100001; //D
4'b1110 : out1=7'b0000110; //E
4'b1111 : out1=7'b0001110; //F
endcase
endmodule
****************************************************************************
Binary to BCD Converter Module in Verilog (CODE-4)
The binarytoBCD module converts a binary number to the corresponding binary coded decimal (BCD) form.For example, when we have an eight-bit binary number 11111111, we cannot show it directly on the seven-segment display.Therefore, we need to obtain every digit as a four-bit binary decimal code.
For example, the corresponding decimal number is 255. Hence, we should have 0010 for decimal two in hundreds digit, 0101 for decimal five in tens digit, and 0101 for five in ones digit.
We provide the Verilog description for binary to BCD converter in (CODE-4)
The module has one input as binary representing the binary number to be converted. Outputs of the module are thos, huns, tens, and ones.
Here, we had to use blocking assignments in behavioral model to keep digit values.
****************************************************************************
(CODE-4)
module binarytoBCD(binary,thos,huns,tens,ones);
input [11:0] binary;
output reg [3:0] thos, huns, tens, ones;
reg [11:0] bcd_data=0;
always @ (binary)
begin
bcd_data = binary;
thos = bcd_data / 1000;
bcd_data = bcd_data % 1000;
huns = bcd_data / 100;
bcd_data = bcd_data % 100;
tens = bcd_data / 10;
ones = bcd_data % 10;
end
endmodule
****************************************************************************
Verilog Description of Debounce Module (CODE-5)
Since buttons are used in all operations in FPGA Boards, we should eliminate their malfunction known as “debouncing.” This problem occurs when physical properties of the button result in more than one button press effect when it is actually pressed once. There are two ways to eliminate debouncing.
· One is using the physical resistor and capacitor circuitry . Although this is a good solution, we should avoid adding discrete circuit elements at this step.
Therefore, the second solution is adding a delay element to the button pressport. We provide the Verilog module performing this operation in (CODE-5)
In (CODE-5),
the inputs to the debounce module are
btn (representing button press)
clk (representing clock signal).
The output of the module is btn_clr which indicates the button press signal without any (possible) debouncing effect.
The module works as follows. The delay parameter is set as 650000. Assume that we feed the Basys3 clock with a frequency 100 MHz that corresponds to 10-ns clock period. Hence, the delay parameter corresponds to 6.5-ms time duration. The module provides clean button press output if it stays unchanged in this time interval.
****************************************************************************
(CODE-5)
module debounce(clk,btn,btn_clr);
input clk;
input btn;
output reg btn_clr;
parameter delay = 650000; //6.5ms delay
integer count=0;
reg xnew=0;
always @(posedge clk)
if (btn != xnew)
begin
xnew <= btn;
count <= 0;
end
else if (count == delay) btn_clr <= xnew;
else count <= count + 1;
endmodule
**************************************************
XDC FILE FOR HAS:(I/O PORTS ASSIGNMENTS WITH EDGE ARTIX 7 FPGA BOARD LVCMOS33)
click 👉 for Reference:xdc file
Description | Input/output | I/O ADDRESS |
| Clk | N11 |
Password eight bit binary: 55H: 01010101 | sw(7) | N1 |
sw(6) | N2 |
sw(5) | N3 |
sw(4) | M1 |
sw(3) | M2 |
sw(2) | M4 |
sw(1) | L4 |
sw(0) | L5 |
Activation signal | btnC | M14 |
Door | BtnU | K13 |
Win1 | btnD | L14 |
Win2 | btnR | L13 |
Win3 | btnL | M12 |
Blinked | Led[1] | J3 |
Alaramed | Led[0] | H3 |
SEGMENT - A | seg[0] | G2 |
SEG-B | seg[1] | G1 |
SEG-C | seg[2] | H5 |
SEG-D | seg[3] | H4 |
SEG-E | seg[4] | J5 |
SEG-F | seg[5] | J4 |
SEG-G | seg[6] | H2 |
RIGHT DIGIT | an[0] | F2 |
MID RIGHT DIGIT | an[1] | E1 |
MID LEFT DIGIT | an[2] | G5 |
LEFT DIGIT | an[3] | G4 |
****************************************************************************
Home Alarm System with sensor interfacing
We can use sensors instead of switches to realize an actual home alarm system. Therefore, we replace switches representing windows and door by proximity sensors. The proximity sensor we picked works as follows. If someone goes in front of the sensor, it provides the output of logic level 0. Otherwise, the output of the sensor is at logic level 1.
Besides these sensors, we also added a movement (PIR) sensor and sound detector to the home alarm system. The output of the movement sensor is at logic level 0. If it senses a movement, this output goes to logic level 1. If the sound detector detects a sound higher than its sensitivity value (threshold), then its output goes to logic level 0. Otherwise, its output stays at logic level 1. Based on these improvements, we provide the final form of the home alarm system in (code -6)
Movement, proximity, and sound sensors all have three pins: VCC, GND, and OUT. They are all supplied by 3.3 V from the Basys3 board. The output of the movement sensor is connected to JB[3]. The proximity sensor output is connected to JB[7]. The sound sensor output is connected to JA[3].
(code -6)
module home_alarm_topmodule(clk,sw,btnC,btnU,led,seg,an,JA,JB,JC);
input clk;
input [7:0] sw;
input btnC, btnU;
output [4:0] led;
output [6:0] seg;
output [3:0] an;
input [3:0] JA;
input [3:7] JB;
output [3:0] JC; //bluetooth JC[2]:rx, JC[3]:tx
wire movement, proximity, sound;
assign movement = JB[3];
assign proximity = ~JB[7];
assign sound = ~JA[3];
assign led [4:2] = {JB[3],JB[7],JA[3]};
wire btnCclr, btnUclr;
debounce_0 dbC(clk,btnC,btnCclr);
debounce_0 dbU(clk,btnU,btnUclr);
home_alarm2_0 alarm1(.clk(clk),.pass(sw),.act(btnCclr),.door(btnUclr),.win1(movement),.win2(proximity),.win3(sound),.blinkled(led[1]),.alarmled(led[0]),.seg(seg),.an(an),.buzzer(JC[0]));
reg [255:0] word= {"A","L","A","R","M",8'h0A};
UART_word_tx_0 TX(clk,led[0],word,6'b000110,JC[2]);
endmodule
👉back to main page
