DICD NOTES

A.Y 2023-24 SEM-2:

CLICK HERE FOR   MID MARKS  

  CLICK HERE 👉😫💥Syllabus DICD  💥💥💥

  CLICK HERE 👉👉💥💥 assignment -1  💥💥💥

CLICK HERE FOR   MID MARKS  

CLICK HERE FOR MID-1 OBJECTIVE QUESTION 

mid-1 imp questions:

Data types

Operators

Data object

Vhdl syntax and modelling styles 

unit-1:👉😫💤💥💢💥💥VHDL material 💥💥💥

previous question papers 👉😫💤💥💢👉💥💥  DIGITAL-IC-DESIGN-JULY-2023 💥💥💥

Unit3

 CLICK HERE FOR COUNTER VHDL

Flip Flops

Register 

CLICK HERE FOR     UNIT-4                                                       

 CLICK HERE FOR     UNIT-5  

CLICK HERE 👉👉💥💥 Assignment -2 💥💥💥

CLICK HERE 👉👉💥💥 MID-2 IMP QUESTIONS 💥💥💥

DIGITAL IC DESIGN

Outcomes:

At the end of this course the student can able to:

CO-1: Learn the Hardware Description Language (VHDL & VERILOG).

CO-2: Understand the structure of commercially available digital integrated circuit families.

CO-3: Analyze and design combinatorial and sequential logic circuits using HDL code.

CO-4: Interpret the digital logic circuits using MOS logic circuits. 

 

 

UNIT-I : Hardware Description Languages.

VHDL: Introduction to VHDL, entity declaration, architecture, data-flow, behavioral and structural style

Of modelings, datatypes, data objects, configuration declaration, package, generic, operators and identifiers, PROCESS, IF, CASE & LOOP statements, VHDL libraries.

 

Verilog HDL: Introduction to Verilog HDL, data types, data operators, module statement, wire statement, if-else statement, case-endcase statement, Verilog syntax and semantics (qualitative approach)

 

UNIT-II: Combinational Logic Design:

Parallel binary adder, carry look ahead adder, BCD adder, Multiplexers And demultiplexers and their use in combinational logic design, ALU, digital comparators, parity generators, code converters, priority encoders. (Qualitative approach of designing and modeling the mentioned Combinational logic circuits with relevant digital ICs using HDL)

 

UNIT-III: Sequential Logic Design:

Registers, applications of shift registers, ripple or a synchronous counters, synchronous counters, synchronous and a synchronous sequential circuits, hazards in sequential circuits.

(Qualitative approach of designing and modeling the mentioned sequential logic circuits with relevant digital ICs using HDL)

 

UNIT-IV: Combinational MOS Logic Circuits:

Introduction, MOS logic circuits with depletion nMOS loads: two-input NOR gate, generalized NOR structure with multiple inputs, transient analysis of NOR gate, two-input NAND gate, generalized NAND structure with multiple inputs, transient analysis of NAND gate, CMOS logic circuits: CMOS NOR2 gate, CMOS NAND2 gate, complex logic circuits, complex CMOS logic gates, AOI and OAI gates, Pseudo-nMOS gates, CMOS full-adder circuit, CMOS transmission gates (Pass Gates),Complementary pass-transistor logic.

 

UNIT-V: Sequential MOS Logic Circuits:

Introduction, behavior bistable elements, SR latch circuit, clocked latch and flip-flop circuits: clocked SR latch, clocked JK latch, master-slave flip-flop, CMOS D-latch and Edge-triggered flip-flop, Schmitt trigger circuit, basic principles of pass transistor circuits.

 

TEXTBOOKS

1. Modern Digital Electronics–R.P.Jain-Fourth Edition–Tata McGraw Hill Education Private Limited,

2010.

2. CMOS Digital Integrated Circuits-Analysis and Design–Sung-MoKang & Yusuf Leblebici-Tata

McGraw Hill Publishing Company Limited, 2006.

3. VHDL/VerilogPrimer - J.Bhasker, Pearson Education/PHI, 3 rd Edition.

 

REFERENCES

1. Digital Design Principles & Practices-John F.Wakerly, PHI/Pearson Education Asia, 3rd Edition,2005.

2. Fundamentals of Digital Logic with VHDL Design - Stephen Brown, Zvonko Vranesic, McGraw

Hill, 3rd Edition.

old post:A.Y 2022-23

 CLICK HERE 👉👉     💥💥💥ASSIGNMENT 1 QUESTION PAPER  💥💥💥

CLICK HERE 👉👉     💥💥💥         Mid-1 important questions         💥💥💥

CLICK HERE 👉👉     💥💥💥         UNIT-1 NOTES