STLD QUESTION BANK & SOLUTION

    

        MID-1 QUESTION BANK

UNIT-1: 

1. Illustrate the operation of two-input AND, OR, NOR, NAND, and XOR gates by drawing their logic symbols, truth tables, and corresponding Boolean expressions. 

Fundamental building blocks in digital electronics which is used to perform logical operations based on the inputs provided to it and gives a logical output that can be either high(1) or low(0).

NOT GATE 

one of the basic logic gate having only a single input and a single output. It is also known as inverter or inverting buffer. When the input signal is "low" the output signal is "high" and vice-versa.

AND GATE: is used to perform logical multiplication of binary input. The Output state of the AND gate will be high (1) if both the input is high (1), else the output state will be low(0) if any of the input is low (0).

The Boolean Expression or logic for the AND gate is the logical multiplication of inputs denoted by a full stop or single dot as :

The value of X will be True when both the inputs will be True

OR GATE

The output state of OR gate will be high i.e., (1) if any of the input state is high or 1, else output state will be low i.e., 0.

The Boolean Expression for the OR gate is the logical addition of inputs denoted by plus sign (+) as

The value of X will be high(true) when one of the inputs is set to high (true).

NOR GATE

The NOR gate is the type of universal logic gate. It takes two or more inputs and gives only one output. The output state of the NOR gate will be high (1) when all the inputs are low (0). NOR gate returns the complement result of the OR gate. It is basically a combination of two basic logic gates i.e., OR gate and NOT gate.

NAND GATE

The NAND Gate is another type of Universal logic gate. The NAND gate or "Not AND" is the combination of two basic logic gates AND gate and the NOT gate connected in series. It takes two or more inputs and gives only one output. The output of the NAND gate will give result high (1) when either of its input is high (1) or both of its input are low (0). In simple, it performs the inverted operation of AND gate.

The Boolean Expression of NAND Gate is as follows:X = (A. B)’

XOR GATE

The XOR gate is a special logic gate used to perform modulo-2 addition. It has two inputs and one output. The output is HIGH (1) only when the inputs are different; otherwise, it is LOW (0). XOR gates are widely used in arithmetic logic circuits, comparators, and error detection systems.

The Boolean expression of XOR Gate is:

X = A’B + AB’ OR X=A XOR B or X=(A ⊕ B)

XNOR GATE

The XNOR is the combination of XOR gate and NOT gate. The output of the XNOR gate is high(1) when both the inputs are high (1) or low(0). In other words, the output of the XNOR gate is high(1) when both the inputs are the same. the XNOR gate can sometimes be called as Equivalence gate. In simple words, The XNOR gate is the complement of the XOR gate.

The following is the Boolean expression of the XNOR gate,

Y = A ⊙ B or Y = AB + A’B’ or Y = (A ⊕ B)’

2. Convert the given binary number 101101.101 into its equivalent decimal and hexadecimal representations. 

binary number TO decimal

(101101.101)₂ = 1·2⁵+1·2³+1·2²+1·2⁰+1·2⁻¹+1·2⁻³

=32+8+4+1+0.5+0.125=45.625₁₀

binary number to Hexa decimal

0010 1101 . 1010₂ = 2D.A₁₆

Answer: (45.625)₁₀ = (2D.A)₁₆

3. Calculate ( A - B) decimal number A=37.42 from B=49.69 by using 9’s complement and 10’s complement methods 

4. Determine the complements of the following Boolean expressions: 

(i) AB+A(B+C)+B’(B+D)                  (ii) A+B+A’B’C 

(i) F=AB+A(B+C)+B'(B+D)

F=AB+AB+AC+B'B+B'D

=AB+AC+B'D

apply complement on both side

F'= (AB+AC+B'D)' (use demorgan law)

=(AB)' . (AC)' . (B'D)'

=(A'+B')(A'+C')(B+D)

(ii) F=A+B+A'B'C

            =A+B+(A'B'C)            (use demorgan law)

apply complement on both side

 F'=( A+B+(A'B'C)  )'

 F'=A' B' (A'B'C)'

F'=A' B' (A''+B''+C')

F'=A' B' (A +B +C') 

             F'=A'B'C'

5. Calculate the product of the octal numbers (23)8 and (12)8, and verify the result by converting it into the decimal number system. 

6. Explain the standard (canonical) SOP and POS forms for a three-variable Boolean function with suitable examples. 

7. Realize XOR and XNOR gates using only NOR gates. Draw the corresponding logic circuits? 

8. Realize XOR and XNOR gates using only NAND gates. Draw the corresponding logic circuits and verify their operation using truth tables. 

9. Encode the decimal number (32.89)10 using 8421, 84-2-1, 2421, Excess-3, and Gray codes. 

10. Calculate the subtraction (569.5-745.3) using 7’s complement and 8’s complement methods. 

11. Explain the significance of the base (radix) of a number system and describe the (r)’s and ((r-1))’s complement methods with suitable examples. 

12. Determine and analyze the value of the base (x) for the following number-system equations: a) (211)x =(152)8 b) (292)10 = (1204)x 

13. Determine the complements of the following Boolean expressions: (i) (AB+A(B+C)+B'(B+D)) (ii) (A+B+A'B'C) 

14. Calculate the product of the binary numbers (1011)2 and (1110)2, and verify the result in the decimal number system. 

15. Convert the following Boolean function into its canonical SOP and POS forms:

 f(A,B,C,D) = ( AB + C) ( B + C'D ) 

16. Explain the different methods used to represent negative numbers in binary and illustrate the representation of signed numbers from (+7) to (-8). 

17. Explain the different methods used to represent negative numbers in the binary number system with suitable examples. 

18. Calculate ( A - B) of binary number A=(1001.101)2 from B=(1101.001)2 using both 1’s complement and 2’s complement methods. 

19. Realize NOT and OR gates using NAND and NOR gates. Draw the corresponding logic circuits? 

20. Explain weighted and non-weighted binary codes and illustrate each type with suitable examples. 21. Convert the given Boolean function into its canonical SOP and POS forms: f= w y + x (w +y zl ) 

22. Calculate (49.69 - 37.42) using both 9’s complement and 10’s complement methods. 

23. Encode the specified decimal numbers using the 6,3,1,-1 weighted code and determine whether the code is self-complementing. Justify your conclusion. 

24. Calculate the product of the hexadecimal numbers ( CA )H and ( E8 )H, and verify the result by converting it into the decimal number system. 

UNIT-2: 

1. Design and develop a BCD-to-Gray code converter using the K-map method and construct its complete logic circuit. 

BY OBSERVATION IN TRUTH TABLE G3 OUTPUT IS EQUAL TO A

SO g3= A

2. Design and develop a BCD-to-Excess-3 code converter using the K-map method and construct its complete logic circuit. 

A BCD-to-Excess-3 code converter is a combinational circuit that transforms a 4-bit Binary Coded Decimal (A, B, C, D)  into its corresponding 4-bit Excess-3 code (E3,E2,E1,E0) by adding binary (0011) i.e.  (3) to each decimal digit. 

LET (A, B, C, D) be the BCD inputs (MSB to LSB) and (E3,E2,E1,E0) be the Excess-3 outputs. For BCD inputs 10 through 15 (decimal 10-15), the outputs are treated as don't-care conditions ( X ) because valid BCD only runs from 0 to 9. 

TRUTH TABLE:

K-Map Simplification and Boolean Expressions

For Output E3:
• Minterms: ∑𝑚(5, 6, 7, 8, 9) + Don't cares ∑𝑚 d(10, 11, 12, 13, 14, 15)
For Output E2:
• Minterms: ∑𝑚(1,2,3,4, 9) + Don't cares ∑𝑚 d(10, 11, 12, 13, 14, 15)
For Output E1:
• Minterms: ∑𝑚(0, 3, 4, 7, 8) + Don't cares ∑𝑚 d(10, 11, 12, 13, 14, 15)
For Output E1:
• Minterms: ∑𝑚(0, 2, 4, 6, 8) + Don't cares ∑𝑚 d(10, 11, 12, 13, 14, 15)

3. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NOR gates: 

f(a,b,c,d,e) = πM(0,2,3,10,12,16,17,18,21,26,27)+ πd(11,13,19,20) 

4. Analyze and simplify the given Boolean function using the K-map method by considering the specified don’t-care conditions, and realize the simplified function using NAND gates: 

F(A, B, C, D) =∑m (4, 5, 7, 12, 13, 14) ∑d (1, 9, 11, 15) 

5. Explain the operation of a Look-Ahead Carry Adder and illustrate its working using a suitable circuit diagram and Boolean expressions. 

6. Analyze the given logic circuit using K-map or Boolean algebra, simplify the corresponding Boolean expressions, and redraw the simplified circuit. 

 7. Analyze the given logic circuit using K-map or Boolean algebra, derive and simplify the expressions for G1, G2, G3, G4, G5, G6 and X, and redraw the simplified circuit ? 

ANALYSIS OF  LOGIC CIRCUIT

Step 1: Identify the outputs of individual gates

From the circuit:

Input Inverters :  C → C′  ,   B→B′

Gate G1

G1 is a NAND gate with inputs $D$ and $C'$.

$$\boxed{G_1=(DC')'}$$

Using De Morgan's theorem:   Out Put  of  G1​=D′+C

Gate G2

G2 is an AND gate with inputs $C'$ and $B'$. Out Put  of  G2​=C′B′

Gate G3

G3 is an OR gate with inputs $A$ and $B'$.  Out Put  is  G3​=A+B′​​

Gate G4

G4 is a NOR gate with inputs $A$ and $B$.

$$\boxed{G_4=(A+B)'}$$

Using De Morgan's theorem:     Out Put  of  G4​=A′B′

Gate G5

G5 is a NOR gate with inputs $G_1$ and $G_2$.

$$G_5=(G_1+G_2)'$$

Substituting: 

$$G_5=\left[(DC')'+C'B'\right]'$$

Using De Morgan's theorem:

$$G_5=(DC')\cdot(C'B')'$$

Now,

$$(C'B')'=C+B$$

Therefore,

$$G_5=DC'(C+B)$$

Expanding:

$$G_5=DC'C+DC'B$$

Since,             C′C=0

$$G_5=0+DBC'$$

Therefore,                                                 G5​=DBC′

Gate G6

G6 is a NAND gate.

$$G_6=(G_3G_4)'$$

Substituting:

$$G_6=\left[(A+B')(A+B)'\right]'$$

We know:

$$(A+B)'=A'B'$$

Therefore,

$$G_6=\left[(A+B')A'B'\right]'$$

Simplifying inside:

$$(A+B')A'B'$$ $$=AA'B'+A'B'B'$$ $$=0+A'B'$$

                                                                                =A′B′

Therefore,

$$G_6=(A'B')'$$

Using De Morgan's theorem:   G6​=A+B

Final Output X

The final gate is an OR gate.

$$X=G_5+G_6$$

Substituting:

$$X=DBC'+(A+B)$$ $$X=A+B+DBC'$$

Using the absorption theorem:

$$B+BX=B$$

Therefore,

$$B+DBC'=B$$

Hence,

                                X=A+B

 

 8. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NAND gates: f( a,b,c,d,e) = ∑m(1,4,8,10,11,20,22,24,25,26) + ∑d(0,12,16,17) 

9. Design and construct a full adder using two half adders. Realize the resulting circuit using NOR gates and develop its functional table. 

10. Analyze the given logic circuit using K-map or Boolean algebra, derive and simplify the expressions for X1, X2, X3, X4 & F, and redraw the simplified circuit ? 

ANALYSIS OF LOGIC CIRCUIT

Gate X1

From the diagram, $X_1$ is a NOR gate whose two inputs are connected to $D$.

Therefore:

$$X_1=(D+D)'$$

Since:

$$D+D=D$$

Therefore:                                                  X1​=D′​

Gate X2

$X_2$ is a NAND gate with inputs $A$ and $B$.

$$X_2=(AB)'$$

Using De Morgan's theorem:                 X2​ =A′+B′

Gate X3

$X_3$ is a 3-input AND gate.

Its inputs are:  B , C, X1

Therefore:

$$X_3=BCX_1$$

Since:

$$X_1=D'$$

Therefore:

X3​=BCD′

Gate X4

$X_4$ is an OR gate.

$$X_4=X_2+X_3$$

Substituting:

$$X_4=(AB)'+BCD'$$

Using:

$$(AB)'=A'+B'$$

Therefore:

X4​=A′+B′+BCD′​ 

Final Output F

The final gate is an OR gate with inputs $X_4$ and $D$.

$$F=X_4+D$$

Substituting:

$$F=A'+B'+BCD'+D$$

Rearranging:

$$F=A'+B'+D+BCD'$$

Using the identity:

$$X+X'Y=X+Y$$

                                                                    D+D′BC=D+BC 

Therefore:

$$F=A'+B'+D+BC$$

Now,

$$B'+BC=B'+C$$

Therefore:

                                                                    F=A′+B′+C+D

 11. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NOR gates: f(a,b,c,d,e) = πM(0,2,3,10,12,16,17,18,21,26,27) + dM(11,13,19,20) 

12. Design and construct a full subtractor using two half subtractors. Realize the resulting circuit using NAND gates and develop its functional table. 

13. Design and develop a Gray-to-binary code converter using the K-map method and construct its complete logic circuit.

A Gray-to-binary code converter is a combinational logic circuit that transforms a 4-bit Gray code input (G3G2G1G0) into its corresponding 4-bit Binary code output (B3B2B1B0).

Decimal Equivalent	Gray Code Inputs (G3G2G1G0)	Binary Outputs (B3B2B1B0)
0	0000	0000
1	0001	0001
2	0010	0011
3	0011	0010
4	0100	0111
5	0101	0110
6	0110	0100
7	0111	0101
8	1000	1111
9	1001	1110
10	1010	1100
11	1011	1101
12	1100	1000
13	1101	1001
14	1110	1011
15	1111	1010

K-Map Simplification and Boolean Expressions

• For Output (B3):
  • Minterms: B3=∑𝑚(8, 9, 10, 11, 12, 13, 14, 15)
• For Output (B2):
  • Minterms: B2=∑𝑚(4, 5, 6, 7, 8, 9, 10, 11)
• For Output (B1):
  • Minterms: B1=∑𝑚(2, 3, 4, 5, 8, 9, 14, 15)
• For Output (B0):
• Minterms: B0=∑𝑚(1, 2, 4, 7, 8, 11, 13, 14)
• Draw the KMap for each output and simplfy, then draw logic circuit

CLASS TEST - 2 

short questions: 

1. Define Karnaugh -map. draw 2,3 variable K-map with min terms and max terms 

Karnaugh Map (K-Map) is a graphical method used to simplify Boolean expressions without using lengthy Boolean algebra. It helps reduce the number of logic gates by grouping adjacent cells in a truth table, making digital circuits simpler and more efficient.

• K-map can be used for SOP and POS forms.
• It organizes truth table values into a grid for easy simplification.

Depending on the required representation, a K-Map is filled with 1s (for SOP) or 0s (for POS), and adjacent cells are grouped to obtain a simplified Boolean expression.

2. Draw half-adder truth table & circuit 

A half adder is a basic combinational circuit that adds two single-bit binary inputs (A and B) to produce a SUM using an XOR gate and a CARRY using an AND gate, without considering any carry-in from a previous stage.

• Performs binary addition of two single-bit inputs, generating a SUM (A ⊕ B) and CARRY (A · B).
• Cannot handle carry-in from a previous stage, making it suitable only for the first stage of multi-bit addition.

• Truth Table of Half Adder

  A	B	Sum	Carry
  0	0	0	0
  0	1	1	0
  1	0	1	0
  1	1	0	1

Sum = A XOR B

Carry = A AND B 

 3. Draw half-subtractor truth table & circuit 

A Half Subtractor is a combinational logic circuit that performs the subtraction of two single-bit binary numbers. It has two inputs (A and B) and produces two outputs: Difference and Borrow.

• Can be implemented using a combination of XOR, AND, and NOT logic gates.
• Acts as the basic building block for designing full subtractors and multi-bit subtraction circuits.
• 
  
  

  Truth Table of Half Subtractor

  A	B	Diff	Borrow
  0	0	0	0
  0	1	1	1
  1	0	1	0
  1	1	0	0

 Difference = A'B + AB' = A ⊕ B

Borrow = A'B

4. What is an prime implicant & essential prime implicant? 

Feature	Prime Implicant (PI)	Essential Prime Implicant (EPI)
Definition	The largest possible valid group of adjacent ones.	A PI that covers at least one unique 1-          cell not covered by any other PI.
In Final Solution	May or may not appear in the final simplified expression.	Always appears in the final simplified      expression.
Uniqueness	Can overlap with other groups entirely.	Contains a distinguished cell unique to it.

 

5. Reduce the following expression using Karnaugh map F= B'A + A'B+AB 

6. Simplify the following to minimum number of literals. 

            (i)A ̅ B(D + C̅D) + B(A ̅ + ACD)                 ii) x̅y+ xy + x̅y 

7. Find the minimized SOP expression for F = Σ(1, 3, 5) & realize using NAND gates. 

 8. Simplify F(A, B, C) = Π(1, 3, 5) & realize using NOR gates.

Long questions: 

1. Design BCD TO GRAY code converter using K Map draw the complete circuit diagram. 

2. Design a 4 bit ADDER/SUBTRACTOR circuit with add/sub control Line 

3. Design full adder using NAND gate explain operation 

4. Implement function using by using only NOR gates f=(w,x,y,z) =∑(0,2,4,9,12,15)+ ∑d(6,7,8,9,11,15) 

5. Design full subtractor using NAND gate explain operation 

6. Obtain the minimal expression by using K-MAP method.

            f( a,b,c,d,e) = ∑m(1,4,8,10,11,20,22,24,25,26) + ∑d(0,12,16,17) 

7. Design and implement a Look-Ahead carry Adder. 

Carry Look-ahead Adder : 
A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. In this design, the ripple carry design is suitably transformed such that the carry logic over fixed groups of bits of the adder is reduced to two-level logic. Let us discuss the design in detail. 

Consider the full adder circuit shown above with corresponding truth table. We define two variables as 'carry generate' $G_i$and 'carry propagate' $P_i$then, 
$$\begin{gathered} P_i=A_i\oplus B_i \\ {G}_i=A_i{B}_i \end{gathered}$$ 

The sum output and carry output can be expressed in terms of carry generate $G_i$and carry propagate $P_i$as

$$\begin{gathered} S_i=P_i\oplus C_i \\ {C}_{i+1}=G_i+P_i{C}_i \end{gathered}$$
where $G_i$produces the carry when both $A_i$, $B_i$are 1 regardless of the input carry. $P_i$is associated with the propagation of carry from $C_i$to $C_{i+1}$. 

The carry output Boolean function of each stage in a 4 stage carry look-ahead adder can be expressed as

$$\begin{gathered} C_1=G_0+P_0{C}_{in} \\ {C}_2=G_1+P_1{C}_1=G_1+P_1{G}_0+P_1{P}_0{C}_{in} \\ {C}_3=G_2+P_2{C}_2=G_2+P_2{G}_1+P_2{P}_1{G}_0+P_2{P}_1{P}_0{C}_{in} \\ {C}_4=G_3+P_3{C}_3=G_3+P_3{G}_2+P_3{P}_2{G}_1+P_3{P}_2{P}_1{G}_0+P_3{P}_2{P}_1{P}_0{C}_{in} \end{gathered}$$

From the above Boolean equations we can observe that $C_4$does not have to wait for $C_3$and $C_2$to propagate but actually $C_4$is propagated at the same time as $C_3$and $C_2$. Since the Boolean expression for each carry output is the sum of products so these can be implemented with one level of AND gates followed by an OR gate.

The implementation of three Boolean functions for each carry output ($C_2$, $C_3$and $C_4$) for a carry look-ahead carry generator shown in below figure. 

NEED FOR Carry Look-ahead Adder 

The adder produce carry propagation delay while performing other arithmetic operations like multiplication and divisions as it uses several additions or subtraction steps. This is a major problem for the adder and hence improving the speed of addition will improve the speed of all other arithmetic operations. Hence reducing the carry propagation delay of adders is of great importance. There are different logic design approaches that have been employed to overcome the carry propagation problem. One widely used approach is to employ a carry look-ahead which solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called a carry look-ahead adder.

Here a carry signal will be generated in two cases:

1. Input bits A and B are 1
2. When one of the two bits is 1 and the carry-in is 1.

Consider the above 4-bit ripple carry adder. The sum $S_3$is produced by the corresponding full adder as soon as the input signals are applied to it. But the carry input $C_4$is not available on its final steady-state value until carry $C_3$is available at its steady-state value. Similarly $C_3$depends on $C_2$and $C_2$on $C_1$. Therefore, though the carry must propagate to all the stages in order that output $S_3$and carry $C_4$settle their final steady-state value. 

The propagation time is equal to the propagation delay of each adder block, multiplied by the number of adder blocks in the circuit. For example, if each full adder stage has a propagation delay of 20 nanoseconds, then $S_3$will reach its final correct value after 60 (20 × 3) nanoseconds. The situation gets worse, if we extend the number of stages for adding more number of bits. 

8. Redraw the given circuit in figure after simplification