ECE_Legends

CLASS TEST - 2

short questions:

1. Define Karnaugh -map. draw 2,3 variable K-map with min terms and max terms

Karnaugh Map (K-Map) is a graphical method used to simplify Boolean expressions without using lengthy Boolean algebra. It helps reduce the number of logic gates by grouping adjacent cells in a truth table, making digital circuits simpler and more efficient.

K-map can be used for SOP and POS forms.
It organizes truth table values into a grid for easy simplification.

Depending on the required representation, a K-Map is filled with 1s (for SOP) or 0s (for POS), and adjacent cells are grouped to obtain a simplified Boolean expression.

2. Draw half-adder truth table & circuit

A half adder is a basic combinational circuit that adds two single-bit binary inputs (A and B) to produce a SUM using an XOR gate and a CARRY using an AND gate, without considering any carry-in from a previous stage.

Performs binary addition of two single-bit inputs, generating a SUM (A ⊕ B) and CARRY (A · B).
Cannot handle carry-in from a previous stage, making it suitable only for the first stage of multi-bit addition.
Truth Table of Half Adder
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Sum = A XOR B

Carry = A AND B

3. Draw half-subtractor truth table & circuit

A Half Subtractor is a combinational logic circuit that performs the subtraction of two single-bit binary numbers. It has two inputs (A and B) and produces two outputs: Difference and Borrow.

Can be implemented using a combination of XOR, AND, and NOT logic gates.
Acts as the basic building block for designing full subtractors and multi-bit subtraction circuits.
Truth Table of Half Subtractor
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

A	B	Diff	Borrow
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Difference = A'B + AB' = A ⊕ B

Borrow = A'B

4. What is an prime implicant & essential prime implicant?

Feature	Prime Implicant (PI)	Essential Prime Implicant (EPI)
Definition	The largest possible valid group of adjacent ones.	A PI that covers at least one unique 1- cell not covered by any other PI.
In Final Solution	May or may not appear in the final simplified expression.	Always appears in the final simplified expression.
Uniqueness	Can overlap with other groups entirely.	Contains a distinguished cell unique to it.

5. Reduce the following expression using Karnaugh map F= B'A + A'B+AB

6. Simplify the following to minimum number of literals.

(i)A ̅ B(D + C̅D) + B(A ̅ + ACD) ii) x̅y+ xy + x̅y

7. Find the minimized SOP expression for F = Σ(1, 3, 5) & realize using NAND gates.

8. Simplify F(A, B, C) = Π(1, 3, 5) & realize using NOR gates.

Long questions:

1. Design BCD TO GRAY code converter using K Map draw the complete circuit diagram.

2. Design a 4 bit ADDER/SUBTRACTOR circuit with add/sub control Line

3. Design full adder using NAND gate explain operation

4. Implement function using by using only NOR gates f=(w,x,y,z) =∑(0,2,4,9,12,15)+ ∑d(6,7,8,9,11,15)

5. Design full subtractor using NAND gate explain operation

6. Obtain the minimal expression by using K-MAP method.

f( a,b,c,d,e) = ∑m(1,4,8,10,11,20,22,24,25,26) + ∑d(0,12,16,17)

7. Design and implement a Look-Ahead carry Adder.

Carry Look-ahead Adder :
A carry look-ahead adder reduces the propagation delay by introducing more complex hardware. In this design, the ripple carry design is suitably transformed such that the carry logic over fixed groups of bits of the adder is reduced to two-level logic. Let us discuss the design in detail.

Click to enlarge

Consider the full adder circuit shown above with corresponding truth table. We define two variables as 'carry generate' $G_{i}$ and 'carry propagate' $P_{i}$ then,
$P_{i} = A_{i} \oplus B_{i} G_{i} = A_{i} B_{i}$

The sum output and carry output can be expressed in terms of carry generate $G_{i}$ and carry propagate $P_{i}$ as

$S_{i} = P_{i} \oplus C_{i} C_{i + 1} = G_{i} + P_{i} C_{i}$
where $G_{i}$ produces the carry when both $A_{i}$ , $B_{i}$ are 1 regardless of the input carry. $P_{i}$ is associated with the propagation of carry from $C_{i}$ to $C_{i + 1}$ .

The carry output Boolean function of each stage in a 4 stage carry look-ahead adder can be expressed as

$C_{1} = G_{0} + P_{0} C_{i n} C_{2} = G_{1} + P_{1} C_{1} = G_{1} + P_{1} G_{0} + P_{1} P_{0} C_{i n} C_{3} = G_{2} + P_{2} C_{2} = G_{2} + P_{2} G_{1} + P_{2} P_{1} G_{0} + P_{2} P_{1} P_{0} C_{i n} C_{4} = G_{3} + P_{3} C_{3} = G_{3} + P_{3} G_{2} + P_{3} P_{2} G_{1} + P_{3} P_{2} P_{1} G_{0} + P_{3} P_{2} P_{1} P_{0} C_{i n}$

From the above Boolean equations we can observe that $C_{4}$ does not have to wait for $C_{3}$ and $C_{2}$ to propagate but actually $C_{4}$ is propagated at the same time as $C_{3}$ and $C_{2}$ . Since the Boolean expression for each carry output is the sum of products so these can be implemented with one level of AND gates followed by an OR gate.

The implementation of three Boolean functions for each carry output ( $C_{2}$ , $C_{3}$ and $C_{4}$ ) for a carry look-ahead carry generator shown in below figure.

NEED FOR Carry Look-ahead Adder

The adder produce carry propagation delay while performing other arithmetic operations like multiplication and divisions as it uses several additions or subtraction steps. This is a major problem for the adder and hence improving the speed of addition will improve the speed of all other arithmetic operations. Hence reducing the carry propagation delay of adders is of great importance. There are different logic design approaches that have been employed to overcome the carry propagation problem. One widely used approach is to employ a carry look-ahead which solves this problem by calculating the carry signals in advance, based on the input signals. This type of adder circuit is called a carry look-ahead adder.

Here a carry signal will be generated in two cases:

Input bits A and B are 1
When one of the two bits is 1 and the carry-in is 1.

Consider the above 4-bit ripple carry adder. The sum $S_{3}$ is produced by the corresponding full adder as soon as the input signals are applied to it. But the carry input $C_{4}$ is not available on its final steady-state value until carry $C_{3}$ is available at its steady-state value. Similarly $C_{3}$ depends on $C_{2}$ and $C_{2}$ on $C_{1}$ . Therefore, though the carry must propagate to all the stages in order that output $S_{3}$ and carry $C_{4}$ settle their final steady-state value.

The propagation time is equal to the propagation delay of each adder block, multiplied by the number of adder blocks in the circuit. For example, if each full adder stage has a propagation delay of 20 nanoseconds, then $S_{3}$ will reach its final correct value after 60 (20 × 3) nanoseconds. The situation gets worse, if we extend the number of stages for adding more number of bits.

8. Redraw the given circuit in figure after simplification

MID-1 QUESTION BANK:

UNIT-1:

1. Illustrate the operation of two-input AND, OR, NOR, NAND, and XOR gates by drawing their logic symbols, truth tables, and corresponding Boolean expressions.

2. Convert the given binary number 101101.101 into its equivalent decimal and hexadecimal representations.

3. Calculate ( A - B) decimal number A=37.42 from B=49.69 by using 9’s complement and 10’s complement methods

4. Determine the complements of the following Boolean expressions:

(i) AB+A(B+C)+B’(B+D) (ii) A+B+A’B’C

5. Calculate the product of the octal numbers (23)8 and (12)8, and verify the result by converting it into the decimal number system.

6. Explain the standard (canonical) SOP and POS forms for a three-variable Boolean function with suitable examples.

7. Realize XOR and XNOR gates using only NOR gates. Draw the corresponding logic circuits?

8. Realize XOR and XNOR gates using only NAND gates. Draw the corresponding logic circuits and verify their operation using truth tables.

9. Encode the decimal number (32.89)10 using 8421, 84-2-1, 2421, Excess-3, and Gray codes.

10. Calculate the subtraction (569.5-745.3) using 7’s complement and 8’s complement methods.

11. Explain the significance of the base (radix) of a number system and describe the (r)’s and ((r-1))’s complement methods with suitable examples.

12. Determine and analyze the value of the base (x) for the following number-system equations: a) (211)x =(152)8 b) (292)10 = (1204)x

13. Determine the complements of the following Boolean expressions: (i) (AB+A(B+C)+B'(B+D)) (ii) (A+B+A'B'C)

14. Calculate the product of the binary numbers (1011)2 and (1110)2, and verify the result in the decimal number system.

15. Convert the following Boolean function into its canonical SOP and POS forms:

f(A,B,C,D) = ( AB + C) ( B + C'D )

16. Explain the different methods used to represent negative numbers in binary and illustrate the representation of signed numbers from (+7) to (-8).

17. Explain the different methods used to represent negative numbers in the binary number system with suitable examples.

18. Calculate ( A - B) of binary number A=(1001.101)2 from B=(1101.001)2 using both 1’s complement and 2’s complement methods.

19. Realize NOT and OR gates using NAND and NOR gates. Draw the corresponding logic circuits? 20. Explain weighted and non-weighted binary codes and illustrate each type with suitable examples. 21. Convert the given Boolean function into its canonical SOP and POS forms: f= w y + x (w +y zl )

22. Calculate (49.69 - 37.42) using both 9’s complement and 10’s complement methods.

23. Encode the specified decimal numbers using the 6,3,1,-1 weighted code and determine whether the code is self-complementing. Justify your conclusion.

24. Calculate the product of the hexadecimal numbers ( CA )H and ( E8 )H, and verify the result by converting it into the decimal number system.

UNIT-2:

1. Design and develop a BCD-to-Gray code converter using the K-map method and construct its complete logic circuit.

2. Design and develop a BCD-to-Excess-3 code converter using the K-map method and construct its complete logic circuit.

3. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NOR gates: f(a,b,c,d,e) = πM(0,2,3,10,12,16,17,18,21,26,27)+ πd(11,13,19,20)

4. Analyze and simplify the given Boolean function using the K-map method by considering the specified don’t-care conditions, and realize the simplified function using NAND gates: F(A, B, C, D) =∑m (4, 5, 7, 12, 13, 14) ∑d (1, 9, 11, 15)

5. Explain the operation of a Look-Ahead Carry Adder and illustrate its working using a suitable circuit diagram and Boolean expressions.

6. Analyze the given logic circuit using K-map or Boolean algebra, simplify the corresponding Boolean expressions, and redraw the simplified circuit.

7. Analyze the given logic circuit using K-map or Boolean algebra, derive and simplify the expressions for G1, G2, G3, G4, G5, G6 and X, and redraw the simplified circuit ?

8. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NAND gates: f( a,b,c,d,e) = ∑m(1,4,8,10,11,20,22,24,25,26) + ∑d(0,12,16,17)

9. Design and construct a full adder using two half adders. Realize the resulting circuit using NOR gates and develop its functional table.

10. Analyze the given logic circuit using K-map or Boolean algebra, derive and simplify the expressions for X1, X2, X3, X4 & F, and redraw the simplified circuit ?

11. Analyze and simplify the following Boolean function using the K-map method and realize the simplified function using NOR gates: f(a,b,c,d,e) = πM(0,2,3,10,12,16,17,18,21,26,27) + dM(11,13,19,20)

12. Design and construct a full subtractor using two half subtractors. Realize the resulting circuit using NAND gates and develop its functional table.

13. Design and develop a Gray-to-binary code converter using the K-map method and construct its complete logic circuit.

ECE_Legends

Sunday, August 30, 2026

STLD QUESTION BANK

Truth Table of Half Adder

Truth Table of Half Subtractor

STLD QUESTION BANK