DICD CMOS

 DICD CMOS

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DIGITAL IC DESIGN USING CMOS (PE-4)

UNIT-I:

MOS Design: Pseudo NMOS Logic – Inverter, Inverter threshold voltage, Output high voltage, Output Low voltage, Gain at gate threshold voltage, Transient response, Rise time, Fall time, Pseudo NMOS logic gates, Transistor equivalency, CMOS Inverter logic.

UNIT-II:

Combinational MOS Logic Circuits: MOS logic circuits with NMOS loads, Primitive CMOS logic gates – NOR & NAND gate, Complex Logic circuits design – Realizing Boolean expressions using NMOS gates and CMOS gates , AOI and OIA gates, CMOS full adder, CMOS transmission gates, Designing with Transmission gates.

UNIT-III:

Sequential MOS Logic Circuits: Behaviour of bistable elements, SR Latch, Clocked latch and flip flop circuits, CMOS D latch and edge triggered flip-flop.

UNIT-IV:

Dynamic Logic Circuits: Basic principle, Voltage Bootstrapping, Synchronous dynamic pass transistor circuits, Dynamic CMOS transmission gate logic, High performance Dynamic CMOS circuits.

UNIT-V:

Interconnect: Capacitive Parasitics, Resistive Parasitics, Inductive Parasitics, Advanced Interconncet Techniques. Semiconductor Memories: Memory Types, RAM array organization, DRAM – Types, Operation, Leakage currents in DRAM cell and refresh operation, SRAM operation Leakage currents in SRAM cells, Flash Memory- NOR flash and NAND flash.

Designing Memory and Array Structures: Introduction, Memory Classification, Memory Architectures and Building Blocks, The Memory Core, Read Only Memories, Non-volatile Read-Write Memories, Read-Write Memories (RAM), Contents Addressable or Associative Memory (CAM), Memory Peripheral Circuitry, The Address Decoders, Sense Amplifiers, Voltage References, Drivers/Buffers, Timing and Control.

Text Books:

1. Digital Integrated Circuits – A Design Perspective, Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, 2nd Ed., PHI.

2. Digital Integrated Circuit Design – Ken Martin, Oxford University Press, 2011.

References:

1. CMOS Digital Integrated Circuits Analysis and Design – Sung-Mo Kang, Yusuf Leblebici, TMH, 3rd Ed., 2011.

2. CMOS VLSI Design – Neil H.E Weste, David harris, Ayan Banerjee 3rd Edition, Pearson

 

Course Outcomes:   After going through this course the student will be able to

1. Understand the concepts of MOS Design.

2. Design and analysis of Combinational and Sequential MOS Circuits.

3. Extend the Digital IC Design to Different Applications.

4. Understand the Concepts of Semiconductor Memories, Flash Memory, RAM array organization.

UNIT-2 IMP QUESTIONS

Q1.    Draw the two input NOR gate logic circuit with depletion nMOS loads and Explain.         

 

Q2.   Explain how to calculate VOH and VOL for two input NOR gate Logic Circuits with

Depletion nMOS Loads.                                                                                                  

 

Q3.    Draw the two input NAND gate logic circuit with depletion nMOS loads and Explain.         

 

Q4.   Explain how to calculate VOH and VOL for Two input NAND gate Logic Circuits with

Depletion nMOS Loads. Also calculate drain current when the output voltage is VOL.                                                                                                                                     

Q5.    Draw the two input CMOS NOR gate logic circuits and Explain its operation.         

 

Q6.   Explain how to calculate switching threshold for two input NOR gate using CMOS

Logic Circuits.                                                                                                                                  

 

Q7.    Explain about Implementation of Complex Boolean functions using nMOS Logic Circuits.         

 

Q8.    Explain about Implementation of Complex Boolean functions using CMOS Logic Circuits.          

 

Q9.    Explain about problem of constructing a minimum-area layout for the complex CMOS

logic gate.                                                                                                                                 

 

Q10. Write short notes on Pseudo-nMOS gate.                                                                                                                                            

 

Q11. What is CMOS transmission gate? Explain its operation.                                                                                                                                           

 

Q12. Explain the DC analysis of the CMOS transmission gate.                                                                                                                                             

 

Q13. Explain about the equivalent resistances of the three operating regions of the

transmission gate.                                                                                                                                 

 

Q14. Explain about Complementary Pass-Transistor Logic (CPL).                                                                                                                                             

                                        UNIT - 3                          

 

Q1.	Explain bistability principle.
Q2.	Explain the operation of CMOS bistable element and its transient analysis.
Q3.	Explain the operation of an SR latch using NOR gates. Implement it with CMOS design.
Q4.	What is the advantage of JK latch over SR latch. Explain the operation of clocked JK-latch.

Q5.    Explain master-slave JK latch in detail.         

 

Q6.    Explain the working of an edge-triggered CMOS master-slave D flip-flop with neat

diagram.                                                                                                                                 

 

Q7.    Mention the basic principle of a pass transistor circuit.         

 

Q8.    Explain the logic 1 transfer in a pass transistor circuit.         

 

Q9.    Explain the logic 0 transfer in a pass transistor circuit.          

 

Q10. Explain charge storage charge leakage at the soft node X during the inactive clock

cycle in an nMOS pass transistor.