Decoders in Verilog

  Decoders in Verilog

The decoder has N inputs and 2^N outputs to cover all input combinations

consider 2:4 decoders with two inputs and four outputs. The output corresponding to a given input will be at logic level 1 all other outputs will be at logic  0 as shown in functional table

The decoder can be constructed by AND and NOT gates. The circuit diagram of the two-to-four decoder as shown below

Circuit diagram of two-to-four decoder

Verilog Description of Two-to-Four Decoder:

Verilog Description of Three-to-Eight Decoder Using case Keyword

Additional example: 3:8 decoder with enable input:

if en= 1 then decoder will works

module decoder3_to_8( in,out, en); input [2:0]  in; input en; output [7:0] out;   reg [7:0] out;   always @( in or en) begin         if (en)         begin           out=8'd0;           case (in)               3'b000: out[0]=1'b1;               3'b001: out[1]=1'b1;               3'b010: out[2]=1'b1;               3'b011: out[3]=1'b1;               3'b100: out[4]=1'b1;               3'b101: out[5]=1'b1;               3'b110: out[6]=1'b1;               3'b111: out[7]=1'b1;               default: out=8'd0;           endcase       end else out=8'b00000000;       end module

 

test bench:

module decoder_tb;

wire [7:0] out;

reg en;

reg [2:0] in;

integer i;

 

decoder3_to_8 dut(in,out,en);

 

initial begin  

$monitor( "en=%b, in=%d, out=%b ", en, in, out);

   for ( i=0; i<8; i=i+1)

        begin

           {en,in}  = i;

            #1;

        end

end

endmodule

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