ASSIGNMENT -1 DSD HDL

                                             Sir C R Reddy College of Engineering, Eluru-7

Dept. of Electronics and Communication Engg.

FIRST Assignment for A.Y: 2020-21 (R19)

 

Sub      : DSD HDL (R193104B)                                                        Submission Date: 05-11-2021

Class   : III/IV B.Tech (ECE), Section- A ,B& C (Sem-I)                  Max Marks     : 5

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submit in A4 sheets 

1.   Write brief notes on architecture FPGA building block?

2.   What are the modelling styles verilog HDL? Explain each model with an example verilog code?

3.   Tabulate all the operators in verilog with operator type, operator symbol, operation performed & no of operands (4 columns)?

4.   Implement a four-bit full adder/subtractor. The user decides on operation type by a control input. When the control input is logic level 1, subtraction will be done. When the control input is logic level 0, addition is done. Implement this device in Verilog.

5.   Deign the four-to-one multiplexer, two-to-four decoder, the four-to-two encoder in Verilog using                   a. case keyword.                     b. if keyword.

 

 

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Course Outcomes:

At the end of this course the student will be able to

1.     Understand the architecture of FPGAs, tools used in modelling of digital design

2.     Analyze and design basic digital circuits with combinatorial and sequential logic circuits

using Verilog HDL.

3.     Model complex digital systems at several levels of abstractions.

4.     Design real time applications such as vending machine and washing machines etc.

 

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