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mid-2 imp questions:
|
Design and implement 6T (or) 8T CMOS D flip-flop
with neat diagram with operation. |
Design
NOR & NAND based JK latch using static
CMOS logic with circuit diagram. |
Dr. Ch. Jayaprakash is an accomplished Associate Professor in the Department of Electronics and Communication Engineering at SASI INSTITUTE OF TECHNOLOGY & ENGINEERING, Eluru, with over 19 years of teaching experience. He earned his Ph.D. in MEMS from KLU and specializes in VLSI, Analog and Digital IC Design, MEMS, and Signal Processing. His academic journey includes a strong focus on both front-end and back-end VLSI design tools such as MentorGraphics, Tanner, and Vivado. Dr. Jayaprakash has published numerous research papers in reputed international journals, with key contributions in the detection of VOC’S using MEMS technology. He has also filed patents. His passion for innovation and education is evident in his continuous contributions to the field.
STLD mid-1 solution https://docs.google.com/document/d/1RkU6RE-COZCG_MY4oCihimX4muc9jJM9/edit?usp=drivesdk&ouid=102051422039972401246...
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