DICD ASSIGNMENT 1& 2 2023

         ASSIGNMENT -2

Form No. IQAC/20(d)-1

	SIR C R REDDY COLLEGE OF ENGINEERING, ELURU Approved by AICTE & Affiliated to JNTUK, Kakinada
	Department of ECE

 

II/IV B.TECH (R20), SEMESTER –II, A.Y. 2023-24
ASSIGNMENT -2
Subject:	DICD (R2022042)
Section:	A, B & C	Marks: 5M
Date of instruction	07/03/2024

 

Note	ANSWER ALL QUESTIONS
S. No	QUESTIONS	Marks	CO	Level
1	Design a half adder using CMOS. Develop an SOP function  using CMOS.      ,	5	3	L3
2	Develop a 2 input OR- gate using Pseudo NMOS. Develop AOI logic using CMOS devices.	5	4	L2
3	Develop a 2 input NAND gate using Depletion load NMOS transistor. Design 2X1 MUX using a pass transistor logic (PTL).	5	4	L3
4	Design Master slave D flip flop using transmission gates(TG). Design a T flip flop using CMOS.	5	4	L3
5	Design and explain NOR based SR latch using CMOS. Design NAND based JK Latch using CMOS logic.	5	4	L3

 

 

CO. NO.	COURSE OUTCOMES
CO1	Learn the Hardware Description Language (VHDL & VERILOG).
CO2	Understand the structure of commercially available digital integrated circuit families.
CO3	Analyze and design combinatorial and sequential logic circuits using HDL code.
CO4	Interpret the digital logic circuits using MOS logic circuits.

 

BLOOMS TAXONOMY LEVEL
L1	L2	L3	L4	L5	L6
Remember	Understand	Apply	Analyze	Evaluate	Create

  

      ASSIGNMENT -1

Form No. IQAC/20(d)-1

	SIR C R REDDY COLLEGE OF ENGINEERING, ELURU Approved by AICTE & Affiliated to JNTUK, Kakinada
	Department of ECE

 

II/IV B.TECH (R20), SEMESTER –II, A.Y. 2022-23
ASSIGNMENT -1
Subject:	DICD (R2022042)
Section:	A, B & C	Marks: 5M
Date of instruction	20/02/2023

 

Note	ANSWER ALL QUESTIONS
S. No	QUESTIONS	Marks	CO	Level
1	Write brief notes on data types, data objects, operators and identifiers in VHDL? Write the differences between Verilog HDL and VHDL?	5	1	L1
2	Give circuit implementation of 4 Bit Ripple adder and Ripple Adder/Subtractor using ones and twos complement method. Write the HDL code	5	3	L2
3	Draw the logic diagram of 74x283 IC and design a 24-bit ripple adder using the same IC.	5	2	L2
4	List out the different Operators available in Verilog HDL. Explain with example? What are the various data types supported by Verilog HDL?	5	1	L1
5	Explain hazards in sequential circuits?	5	3	L2

 

 

CO. NO.	COURSE OUTCOMES
CO1	Learn the Hardware Description Language (VHDL & VERILOG).
CO2	Understand the structure of commercially available digital integrated circuit families.
CO3	Analyze and design combinatorial and sequential logic circuits using HDL code.
CO4	Interpret the digital logic circuits using MOS logic circuits.

 

BLOOMS TAXONOMY LEVEL
L1	L2	L3	L4	L5	L6
Remember	Understand	Apply	Analyze	Evaluate	Create