Digital Safe System(using sequential circuit)

                         Digital Safe System(using sequential circuit)

In improved the digital safe system.

The user will have chance to enter his or her password instead of a fixed initial

value.

This module has five inputs.

·       clk (main clock signal),  

·       passinput (16-bit password)

·       pass_set (input to change password),

·       pass_reg (input to save new password)

·       pass_lock (to lock safe again after the password change).

The output of the module is a two-bit vector safestate. This output indicates the state of lock, such that

00 shows locked;

01 indicates open;

10 represents enter new password;

11 shows new password set.

 

Working principles of digital safe module (as a state machine) are as follows. The state machine has two states: ENTERPASS and SETPASS.

In ENTERPASS state, the machine checks whether the input matches the password.

If this is the case, safestate changes to 01 which shows that lock is open. Besides, if pass_set is at logic level 1, then state of the machine goes to SETPASS where the new password is entered. After the user determines a new password, pass_reg should go to logic level 1 to save it. Then, pass_lock should go to logic level 1 to lock the safe again.

We provide the modified Verilog description for the digital safe module

in CODE-1.

 

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CODE-1

module digital_safe2(clk,passinput,pass_set,pass_reg,pass_lock,safestate);

input   clk;

input   [15:0]   passinput;

input   pass_set,pass_reg,pass_lock;

output   reg [1:0]   safestate;

//00:locked(c), 01:open(o), 10:enterpass, 11:pass changed(s)

 

localparam   ENTERPASS=1'b0,SETPASS=1'b1;

reg   [1:0]  state=ENTERPASS;

reg   [15:0]  pass=16'h1234;

always @ (posedge clk)

case(state)

ENTERPASS:     

            if (passinput == pass && pass_set == 1'b1)

            begin

            state <= SETPASS;

            safestate <= 2'b10;

            end

            else if (passinput == pass)

            safestate <= 2'b01;

            else safestate <= 2'b00;

SETPASS:

            if (pass_reg == 1'b1)

            begin

            pass <= passinput;

            safestate <= 2'b11; end

            else if (pass_lock == 1'b1)

            state <= ENTERPASS;

endcase

endmodule

 

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We can further improve the digital safe system to be implemented on the

FPGA board.

Here, we can show state of the lock and the new password on the seven-segment display. To do so, we should add the seven-segment display module as an IP block.

Inputs of the digital safe module will be connected to buttons and switches on the FPGA board. Hence, we should also add the debounce module as an IP block.

In CODE-2  pass_set, pass_reg, and pass_lock inputs are assigned to btnU, btnD, and btnC of the Basys3 board respectively. Sixteen switches are used as passinput. The master clock of the board is connected to clk signal.

The output safestate of the digital safe module is kept in a vector with the same name to control the seven-segment display on the board. Hence, when safestate is at 00 all four seven-segment display digits will show character C which stands for “Close”. When safestate is at 01, all display digits will show the character O which stands for “Open”. When safestate is at 11, all digits will show the character S which stands for “Set”. In the 01 state (referring to the password change), digits show the password while the user changes it.

 

We provide the top module for this application in CODE-2

.

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CODE-2

module digital_safe_topmodule(clk,sw,btnC,btnU,btnD,led,an,seg);

 

input   clk;

input   [15:0]   sw;

input   btnC,btnU,btnD;

output   [1:0]   led;

output   [3:0]   an;

output   [6:0]   seg;

 

wire btnCclr,btnDclr,btnUclr;

 

debounce_0  dbc(clk,btnC,btnCclr);

debounce_0  dbu(clk,btnU,btnUclr);

debounce_0  dbd(clk,btnD,btnDclr);

 

reg   [3:0]  disp1=4'b0;

reg   [3:0]  disp2=4'b0;

reg   [3:0] disp3=4'b0;

reg   [3:0] disp4=4'b0;

 

sevenseg_driver_0  seg7(clk,1'b0,disp1,disp2,disp3,disp4,seg,an);

 

wire   [1:0]  safestate;

 

digital_safe2_0   ds(.clk(clk),.passinput(sw),.pass_set(btnUclr),.pass_reg(btnDclr),.pass_lock(btnCclr),.safestate(safestate));

 

always @ (posedge clk)

case(safestate)

2'b00 : {disp1,disp2,disp3,disp4} <= {4{4'b1100}}; //C

2'b01 : {disp1,disp2,disp3,disp4} <= {4{4'b0000}}; //0

2'b10 : {disp1,disp2,disp3,disp4} <= sw;

2'b11 : {disp1,disp2,disp3,disp4} <= {4{4'b0101}}; //S

endcase

 

assign led = safestate;

 

endmodule

 

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Digital Safe System(FINAL MODULE)

We can finalize the digital safe system by adding a USB keyboard to it.Besides, the digital safe will work as explained in CODE 1 &2. We provide the modified and final form of the digital safe in CODE-3.

Let’s explain the working principles of the digital safe system (as a state machine) step by step. The system starts with a default password 1234. When the user enters it, the safe opens. Here, user has two options. The first one is changing the password. The second one is locking the safe again. When btnC on the Basys3 board is pressed, the safe locks again. If the user presses btnU, digital safe goes to the password changing state. Here, it expects the user to enter a new password. This can be done by using numbers on the keyboard. Since this is a prototype system, the entered password is also shown on the seven-segment display (and LEDs) of Basys3.When a new password is entered, the user should press btnD to save it. Afterward, btnC should be pressed to lock the safe again. While entering the password digits, the user may press btnR anytime to restart again.

 

 

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CODE-3

 

module digital_safe_topmodule(clk,btnU,btnC,btnD,btnR,PS2Data,PS2Clk,seg,an,led);

 

input clk;

input btnC,btnU,btnD,btnR;

input PS2Data;

input PS2Clk;

output [3:0] an;

output [6:0] seg;

output [15:0] led;

 

wire btnCclr,btnDclr,btnUclr,btnRclr;

 

debounce_0 dbc(clk,btnC,btnCclr);

debounce_0 dbu(clk,btnU,btnUclr);

debounce_0 dbd(clk,btnD,btnDclr);

debounce_0 dbr(clk,btnR,btnRclr);

 

reg [3:0] disp1;

reg [3:0] disp2;

reg [3:0] disp3;

reg [3:0] disp4;

 

sevenseg_driver_0 seg7(clk,1'b0,disp1,disp2,disp3,disp4,seg,an);

 

wire [1:0] safestate;

reg [15:0] password;

 

digital_safe2_0 safe1(.clk(clk),.passinput(password),.pass_set(btnUclr),.pass_reg(btnDclr),.pass_lock(btnCclr),.safestate(safestate));

 

wire keyready;

reg keyready_prev;

reg [1:0] keystate=0;

wire [7:0] keyout;

 

keypad_app_0 key1(.clk(clk),.PS2Clk(PS2Clk),.PS2Data(PS2Data),.keyout(keyout),.ready(keyready));

 

always @ (posedge clk)

begin

keyready_prev <= keyready;

if (btnRclr) keystate <= 2'b0;

else if (btnCclr == 1'b1) password <= 16'b0;

else

 

case (keystate)

2'b00:     

          if (keyready_prev == 0 && keyready == 1) begin

          password[15:12] <= keyout;

          keystate <= keystate + 1'b1;

          end

2'b01:

          if (keyready_prev == 0 && keyready == 1) begin

          password[11:8] <= keyout;

          keystate <= keystate + 1'b1;

          end             

2'b10:     

          if (keyready_prev == 0 && keyready == 1) begin

          password[7:4] <= keyout;

          keystate <= keystate + 1'b1;

          end

2'b11:

          if (keyready_prev == 0 && keyready == 1) begin

          password[3:0] <= keyout;

          keystate <= 2'b00;

          end

endcase

end

 

always @ (posedge clk)

case(safestate)

          2'b00: {disp1,disp2,disp3,disp4} <= {4{4'b1100}}; //C

          2'b01: {disp1,disp2,disp3,disp4} <= {4{4'b0000}}; //0

          2'b10: {disp1,disp2,disp3,disp4} <= password;

          2'b11: {disp1,disp2,disp3,disp4} <= {4{4'b0101}}; //S

endcase

 

assign led = password;

 

endmodule

 

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