Decoders in Verilog

  Decoders in Verilog

The decoder has N inputs and 2^N outputs to cover all input combinations

consider 2:4 decoders with two inputs and four outputs. The output corresponding to a given input will be at logic level 1 all other outputs will be at logic  0 as shown in functional table

The decoder can be constructed by AND and NOT gates. The circuit diagram of the two-to-four decoder as shown below

Circuit diagram of two-to-four decoder

Verilog Description of Two-to-Four Decoder:

Verilog Description of Three-to-Eight Decoder Using case Keyword

Additional example: 3:8 decoder with enable input:

if en= 1 then decoder will works

module decoder3_to_8( in,out, en); input [2:0]  in; input en; output [7:0] out;   reg [7:0] out;   always @( in or en) begin         if (en)         begin           out=8'd0;           case (in)               3'b000: out[0]=1'b1;               3'b001: out[1]=1'b1;               3'b010: out[2]=1'b1;               3'b011: out[3]=1'b1;               3'b100: out[4]=1'b1;               3'b101: out[5]=1'b1;               3'b110: out[6]=1'b1;               3'b111: out[7]=1'b1;               default: out=8'd0;           endcase       end else out=8'b00000000;       end module

 

test bench:

module decoder_tb;

wire [7:0] out;

reg en;

reg [2:0] in;

integer i;

 

decoder3_to_8 dut(in,out,en);

 

initial begin  

$monitor( "en=%b, in=%d, out=%b ", en, in, out);

   for ( i=0; i<8; i=i+1)

        begin

           {en,in}  = i;

            #1;

        end

end

endmodule

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Comparators in Verilog

 Comparators in Verilog

To compare the magnitude of two binary numbers to obtain their status, as 

• The first number may be greater than the second.
• The two numbers may be equal. Or, 
• The first number may be less than the second. 

To do this we will need a comparator. We can explain the comparison operation on two binary variables x and y (each being one bit) using the truth table presented in Table. Here, g, e, and l stand for greater, equal, and less, respectively.

we can obtain logic functions between inputs and outputs of the one-bit comparator as follows

logic functions lead to the circuit diagram of the one-bit comparator as

Verilog Description of One-Bit Comparator:

The Verilog description of an N-bit comparator to compare two N-bit numbers using dataflow and structural modelling will be complex. Therefore, behavioural modelling will be more appropriate for this case. 

To do so, we need to introduce relational operators and conditional statements in Verilog.

👉👀 relational operators.

An N-bit comparator can be constructed by the if keyword. We provide such a Verilog description only for behavioural modelling

Verilog Description of Four-Bit Comparator Using if Keyword

example 2: using conditional statement

module magComp ( In1, In2, Gt, Lt, Eq );

input [7:0] In1, In2; //The two 8-bit Inputs In1 and In2

output Gt, Lt, Eq; //The Outputs of comparison

reg Gt, Lt, Eq;

always @ (In1 or In2) //Check the state of the input lines

begin

Gt <= ( In1 > In2 )? 1'b1 : 1'b0;

Lt <= ( In1 < In2 )? 1'b1 : 1'b0;

Eq <= ( In1 == In2)? 1'b1 : 1'b0;

end

endmodule

 Verilog Test-bench for 8-bit Magnitude Comparator

`timescale 1ns / 1ps

 

module magComp_tb;

 

 // Inputs

 

 reg [7:0] In1;

 

 reg [7:0] In2;

 

 // Outputs

 

 wire Gt;

 

 wire Lt;

 

 wire Eq;

 

 // Instantiate the Unit Under Test (UUT)

 

magComp uut ( .In1(In1), .In2(In2), .Gt(Gt), .Lt(Lt), .Eq(Eq) );

 

 initial begin

 

  // Initialize Inputs

 

  In1 = 8'b0;

 

  In2 = 8'b0;

 

  // Wait 100 ns for global reset to finish

 

  #100;       

 

  // Add stimulus here

 

  In1 = 8'd8;

 

  In2 = 8'd7;

 

  #20;

 

  In1 = 8'd100;

 

  In2 = 8'd120;

 

  #20;

 

  In1 = 8'd250;

 

  In2 = 8'd250;

 

  #20;

 

  In1 =  8'd0;

 

  In2 = -8'd5;

 

  #20;

 

  In1 = -8'd5;

 

  In2 = -8'd5;

 

  #20;

 

 end

 

endmodule

 simulation result:

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