Friday, August 29, 2025

STLD OBJECTIVE QUESTION 1

 STLD MID I MCQ 



UNIT-I: Review of Number Systems & Codes & Boolean Algebra & Logic Operations

1What is the radix of the hexa decimal number system?

a) 2 b) 8 c) 10 d) 16

Answer: d) 16

2Which code represents each decimal digit with a 4-bit binary code?

a) Gray code b) Excess-3 code c) BCD code d) 2421 code

Answer: c) BCD code

3How is Gray code different from binary code?

a) It uses more bits. b) Adjacent code values differ by only one bit.

c) It is a weighted code. d) It is primarily used for error detection.

Answer: b) Adjacent code values differ by only one bit.

4Which type of parity checking adds a bit to make the total number of 1s even?

a) Odd parity b) Even parity c) Hamming code d) Cyclic Redundancy Check

Answer: b) Even parity

5What is the purpose of Hamming code?

a) Error detection only b) Error correction only 

c) Error detection and correction d) Data compression

Answer: c) Error detection and correction

6Which Boolean theorem states that A+(B+C)=(A+B)+C

a) Commutative Law b) Associative Law c) Distributive Law d) De Morgan's Theorem

Answer: b) Associative Law

7The principle of duality in Boolean algebra involves interchanging which operations and constants?

a) AND and OR, 0s and 1s b) NOT and XOR, As and A's

c) NAND and NOR, inputs and outputs d) SOP and POS forms

Answer: a) AND and OR, 0s and 1s

8According to De Morgan's theorem, (A⋅B)′is equivalent to:

a) A′+B′ b) A′⋅B′ c) A+B d) A⋅B

Answer: a) 𝐴′+𝐵′

9Which of the following is considered a universal logic operation?

a) OR b) AND c) NOT d) NAND

Answer: d) NAND

10What is the standard form that represents a Boolean expression as a sum of product terms?

a) POS b) SOP c) NAND-NAND d) NOR-NOR

Answer: b) SOP

11What is the 1's complement of the binary number 10110?

a) 01001 b) 01010 c) 10101 d) 11001

Answer: a) 01001

12What is the 2's complement of the binary number 10110?

a) 01001 b) 01010 c) 10101 d) 11001

Answer: b) 01010

13The Excess-3 code for decimal digit 5 is:

a) 0101 b) 1000 c) 0010 d) 1011

Answer: b) 1000

14How many bits are required to represent a hexadecimal digit?

a) 2 b) 3 c) 4 d) 8

Answer: c) 4

15If a binary number is converted to Gray code, how many bits differ between adjacent code words?

a) All bits b) Two bits c) One bit d) Zero bits

Answer: c) One bit

16Which code is a self-complementing BCD code?

a) 8421 code b) Gray code c) Excess-3 code d) 2421 code

Answer: c) Excess-3 code

17The expression for De Morgan's theorem for OR operation is:

a) (𝐴+𝐵)′=𝐴′⋅𝐵′ b) (𝐴⋅𝐵)′=𝐴′+𝐵′ c) 𝐴+𝐵=𝐵+𝐴 d) 𝐴⋅(𝐵+𝐶)=𝐴⋅𝐵+𝐴⋅𝐶

Answer: a) (𝐴+𝐵)′=𝐴′⋅𝐵′

18Which logic gate outputs a HIGH only when all inputs are HIGH?

a) OR b) NOR c) AND d) XOR

Answer: c) AND

19Which logic gate is obtained by inverting the output of an OR gate?

a) AND b) NAND c) NOR d) XOR

Answer: c) NOR

20What is the main advantage of using NAND-NAND and NOR-NOR realizations?

a) Reduced complexity of circuits b) Easier to implement universal gates

c) Reduced power consumption d) Fewer gates required compared to other realizations

Answer: d) Fewer gates required compared to other realizations

UNIT-II: Minimization Techniques & Combinational Logic Circuits Design

1What is the maximum number of variables a K-Map can efficiently minimize according to the text?

a) 4 b) 5 c) 6 d) 8

Answer: c) 6

2The Quine-McCluskey method is also known as the:

a) Graphical method b) Tabular method

c) Boolean algebra method d) Karnaugh map method

Answer: b) Tabular method

3A Half Adder circuit is used to add:

a) Three binary bits b) Two binary bits

c) Four binary bits d) Multiple binary numbers

Answer: b) Two binary bits

4How many inputs does a Full Adder take?

a) One b) Two c) Three d) Four

Answer: c) Three

5Which circuit is used to find the difference between two single binary digits?

a) Full Adder b) Half Subtractor c) Full Subtractor d) BCD Adder

Answer: b) Half Subtractor

6 A 4-bit adder-subtractor circuit can perform:

a) Only addition b) Only subtraction c) Both addition and subtraction d) Multiplication

Answer: c) Both addition and subtraction

7 What is the primary advantage of a carry look-ahead adder?

a) Reduces power consumption b) Increases propagation delay

c) Reduces propagation delay d) Simplifies circuit design

Answer: c) Reduces propagation delay

8 In K-map minimization, a group of 8 adjacent 1s eliminates how many variables?

a) 1 b) 2 c) 3 d) 4

Answer: c) 3

9 The Quine-McCluskey method is particularly useful for minimizing Boolean functions with:

a) Few variables b) Many variables c) Only two variables d) Only one output

Answer: b) Many variables

10 Which combinational circuit is used to add two BCD numbers?

a) Full Adder b) Ripple Carry Adder c) BCD Adder d) Excess-3 Adder

Answer: c) BCD Adder

11 How many inputs does a Half Subtractor have?

a) 1 b) 2 c) 3 d) 4

Answer: b) 2

12 What is the output of a Half Subtractor?

a) Sum and Carry b) Difference and Borrow

c) Sum and Difference d) Carry and Borrow

Answer: b) Difference and Borrow

13 Which circuit is a modified BCD adder that works with Excess-3 code inputs?

a) Ripple Carry Adder b) Carry Look-Ahead Adder

c) Excess-3 Adder d) Parallel Adder

Answer: c) Excess-3 Adder

14To realize a three-level logic circuit, which forms can be used?

a) Only SOP b) Only POS c) NAND-NAND or NOR-NOR d) Universal gates only

Answer: c) NAND-NAND or NOR-NOR

15 The main goal of minimization techniques in digital logic is to:

a) Increase circuit complexity b) Reduce the number of gates

c) Increase propagation delay d) Use more components

Answer: b) Reduce the number of gates

16 Which method is suitable for minimizing switching functions with up to 6 variables?

a) Quine-McCluskey method b) K-Map

c) Boolean theorems only d) Tabular method only

Answer: b) K-Map

17 What is the sum output of a Half Adder with inputs A and B?

a) 𝐴⋅𝐵 b) 𝐴+𝐵 c) 𝐴⊕𝐵 d) 𝐴′+𝐵′

Answer: c) 𝐴⊕𝐵

18 The carry output of a Half Adder with inputs A and B is:

a) 𝐴⋅𝐵 b) 𝐴+𝐵 c) 𝐴⊕𝐵 d) 𝐴′+𝐵′

Answer: a) 𝐴⋅𝐵

19 The design of a 4-bit adder-subtractor circuit relies on using:

a) Half Adders b) Full Subtractors c) Full Adders d) Universal gates

Answer: c) Full Adders

20 What is the primary characteristic of a combinational logic circuit?

a) Output depends on present and past inputs b) Contains memory elements

c) Output depends only on present inputs d) Used for sequential operations

Answer: c) Output depends only on present inputs



Tuesday, August 5, 2025

critical thinking practice problems

GROUP -A

1. Smart Elevator Control Logic

A smart elevator controller has 4 binary sensors:

  • F: Floor requested (0 = even floor, 1 = odd floor)

  • O: Overload sensor (0 = not overloaded, 1 = overloaded)

  • D: Door open (0 = closed, 1 = open)

  • E: Emergency button (0 = normal, 1 = emergency)

The elevator should start moving (output = 1) only under the following rules:

  • It is not overloaded, and

  • The door is closed, and

  • Either:

    • A valid floor request is made, or

    • Emergency mode is activated

Frame the minimized logic expression that controls movement.


🔹 2. Industrial Fan Safety System

In a chemical plant, a fan must be automatically turned ON when dangerous conditions arise.
Inputs:

  • T = 1 if Temperature > 70°C

  • G = 1 if Gas leakage is detected

  • P = 1 if Power is available

  • M = 1 if Manual override is enabled

The fan should turn on if:

  • Either T or G is high, and P is available,

  • Or if the manual override (M) is used (regardless of other inputs).

Design the minimized Boolean function to control the fan operation.


🔹 3. Smart Traffic Light Control (4-Way Intersection)

Sensors detect traffic at four roads (A, B, C, D) entering a junction.
Each sensor = 1 if traffic is detected, 0 otherwise.

A special green signal is triggered only if:

  • At least three roads have traffic, and

  • Road D has no traffic (priority to other directions).

Determine the minimal logic expression to control this special green signal.


🔹 4. Smart Irrigation Controller

Inputs:

  • M = Moisture level low (1 = dry)

  • R = Rain sensor (1 = rain)

  • T = Timer condition met (1 = scheduled time)

  • O = Operator override (1 = force on)

The irrigation pump must turn ON when:

  • Moisture is low AND it is scheduled time,

  • But NOT if rain is detected,

  • Unless overridden by the operator.

Design and minimize the logic for the Pump ON signal.


🔹 5. Secure Access System – Restricted Logic

A door lock uses a 4-bit input (A, B, C, D) from a keypad. Only the following binary codes are valid to unlock the door:
0001, 0100, 1010, 1100, 1110, 1111
Other codes do not unlock the door.
Design the simplest logic function that outputs 1 for valid unlock attempts.
Also, use don't care conditions for 0000 and 1000, which are never generated.


🔹 6. Medical Device Alarm Logic

Inputs from sensors in a patient-monitoring device:

  • H = Heart rate abnormal

  • B = Blood pressure abnormal

  • T = Temperature abnormal

  • S = Sleep mode enabled

An alarm should activate only when:

  • Any two or more vitals are abnormal, and

  • Sleep mode is not enabled.

Write the Boolean function and minimize it to reduce logic hardware.


🔹 7. Data Transmission Fault Detection

A 4-bit checksum monitor system detects a fault when:

  • The XOR of all bits is 1 (odd parity), and

  • At least one bit is 1 (to ignore all-zero idle line)

Input bits: A, B, C, D
Design the logic for the Fault flag, and simplify the expression using grouping techniques.


 

GROUP -B

1. Complex Input Combinations (4 variables):

A digital security system uses four binary inputs A, B, C, and D. The output alarm is triggered (i.e., output = 1) for the following input states:
0, 2, 3, 6, 7, 8, 10, 11, 12, 13 (decimal values).
Additionally, the system designer notes that inputs 1 and 9 can never occur in practice.
Derive the most efficient logic expression to activate the alarm.


2. POS-type Minimization – Implied:

A logic function is 0 (false) for the input decimal values:
0, 1, 2, 5, 8, 9, 10, 14
For all other inputs (3, 4, 6, 7, 11, 12, 13, 15), the output is 1.
Find the minimized logic expression that defines this behavior.


3. Mixed Minterms with Don’t Care:

In a certain controller design, the output is 1 for the following binary combinations (decimal):
1, 3, 7, 11, 15
The combinations 0, 2, 5, 13 are considered irrelevant and may take either 0 or 1 (don’t care).
Find the most compact logic equation representing this output behavior.


4. Gray Code Sensitive System:

A system activates an output when the Gray code of a 3-bit input is one of the following:
000, 001, 011, 010 (in binary)
Determine the minimized Boolean expression for this output condition, using inputs A, B, and C where A is the MSB.


5. Pattern Recognition Function:

Design a logic function F(A, B, C, D) such that it outputs 1 only when the binary input represents a prime number less than 16 (i.e., 2, 3, 5, 7, 11, 13).
Derive the minimized Boolean expression to implement this logic.


6. Parity Detection with Conditions:

You have a 4-bit input (W, X, Y, Z).
The output should be 1 if the number of 1s in the input is odd, but only when W = 1.
Minimize the logic expression accordingly.


7. Unusual Grouped Logic Activation:

A logic circuit outputs high for inputs with the decimal values:
0, 1, 5, 7, 9, 11, 13, 15
Find the most efficient Boolean expression to represent this function.
Note: Direct SOP writing leads to long expressions; simplify optimally.


8. Dual Output Function Design:

Design two output functions F1 and F2 from 4 inputs A, B, C, D such that:

  • F1 = 1 for minterms {0, 2, 5, 6, 8, 10, 13}

  • F2 = 1 for maxterms {1, 4, 7, 9, 12, 14, 15}
    Find minimal Boolean expressions for both functions, using any valid technique.


GROUP -C

1.

A digital circuit has three inputs A, B, and C. The output F is high (1) for the following input combinations:

  • A=0, B=0, C=0

  • A=0, B=1, C=0

  • A=1, B=0, C=0

  • A=1, B=1, C=0

Minimize the Boolean expression for F using a systematic approach.


2.

A function F(A, B, C) is true for input combinations corresponding to the decimal values 1, 3, 5, and 7.
Determine the simplest Boolean expression for F.


3.

A certain logic function outputs 1 for the binary inputs:

  • 0001

  • 0011

  • 0111

  • 1111

Assume the inputs are D, C, B, A (in that order). Derive the minimized expression for the output function.


4.

A circuit takes four inputs W, X, Y, Z and gives output 1 only for the decimal inputs 0, 2, 5, 7, 8, 10, 13, and 15.
Find the minimized Boolean expression for the output function.


5.

A digital system defines an output function that is high when the input is in the set {4, 5, 6, 7, 12, 13, 14, 15} and low otherwise.
Find the most simplified expression for this output.


6.

Given a truth table with inputs A, B, C, D, the output is 1 for the minterms:
(1, 3, 7, 11, 15).
Simplify the Boolean function using grouping techniques.


7.

A certain digital logic circuit uses three inputs A, B, and C. The output is high for all input combinations where the number of 1s in the input is even (including zero).
Determine the minimal logic expression for this output.


8.

A control signal is active (1) when the inputs (A, B, C, D) match the binary representations of the decimal values 2, 3, 6, 7, 10, 11, 14, 15.
Write the minimized Boolean expression for this control signal.

STLD UNIT 2

 

L16: K-MAP INTRODUCTION 2, 3 VARIABLE

                                                                                                      Click Here For   Video Lecture 16
L17: KMAP 3 VARIABLES, KMAP 4 VARIABLES, EXAMPLE PROBLEMS ON KMAP 3,4 VARIABLES
                                                                                                      Click Here For   Video Lecture 17

L18:K MAP 4 VARIABLE WITH DONT CARE CONDITIONS(X)
                                                                                                      Click Here For   Video Lecture 18

L19:5 VARIABLE KMAP WITH POS AND SOP MINIMIZATION
                                                                                                      Click Here For   Video Lecture 19
L20:MINIMIZATION AND REALIZATION
                                                                                                      Click Here For   Video Lecture 20


Sunday, July 27, 2025

Subtractions & K Map Practice questions

 All  the students are informed complete the assignment for K MAP both in POS & SOP, realize using NAND & NOR gates

24B81A0401
a) Simplify F(A, B, C) = Σ(0, 2, 4, 6) realize using NAND & NOR gates
b) Subtract 245 - 123 using 9's & 10’s complement.

24B81A0402
b)Find the minimized SOP expression for 
    F = Σ(1, 3, 5) & realize using NAND & NOR gates.    
a) Subtract 370 - 198 using 9's & 10’s complement.

24B81A0403
a) Use K-Map to simplify F = Σ(0, 1, 2, 3)& realize using NAND & NOR gates.
b) Subtract 120 - 389 using 9's & 10’s complement.

24B81A0404
b) Derive minimal expression for F = Σ(2, 3, 6)& realize using NAND & NOR gates.
a) Subtract 684 - 159 using 9's & 10’s complement.

24B81A0405
a) Find SOP form for F = Σ(0, 4, 5, 6)& realize using NAND & NOR gates.
b) Subtract 200 - 450 using 9's & 10’s complement.

24B81A0406
b) Simplify F = Σ(0, 1, 4)& realize using NAND & NOR gates.
a) Subtract 999 - 321 using 9's & 10’s complement.

24B81A0407
a) Use K-Map to simplify F = Σ(1, 2, 4, 7)& realize using NAND & NOR gates.
b) Subtract 805 - 607 using 9's & 10’s complement.

24B81A0408
b) Derive minimal SOP form for F = Σ(3, 5, 7)& realize using NAND & NOR gates.
a) Subtract 431 - 431 using 9's & 10’s complement.

24B81A0409
a) Find simplified function for F = Σ(0, 1, 5, 6)& realize using NAND & NOR gates.
b) Subtract 300 - 150 using 9's & 10’s complement.

24B81A0410
b) Use K-Map to simplify F = Σ(2, 3, 4, 5)& realize using NAND & NOR gates.
a) Subtract 111 - 777 using 9's & 10’s complement.

24B81A0411
a) Simplify F(A, B, C) = Π(1, 3, 5)& realize using NAND & NOR gates.
b) Subtract 236 - 142 using 9's & 10’s complement.

24B81A0412
b) Minimize F = Π(0, 2, 4, 6)& realize using NAND & NOR gates.
a) Subtract 415 - 215 using 9's & 10’s complement.

24B81A0413
a) Derive POS form for F = Π(2, 3, 6)& realize using NAND & NOR gates.
b) Subtract 150 - 389 using 9's & 10’s complement.

24B81A0414
b) Simplify F = Π(0, 4, 5, 6)& realize using NAND & NOR gates.
a) Subtract 822 - 313 using 9's & 10’s complement.

24B81A0415
a) Use K-Map to simplify F = Π(0, 2, 3, 7)& realize using NAND & NOR gates.
b) Subtract 290 - 190 using 9's & 10’s complement.

24B81A0416
b) Simplify using K-Map: F = Π(1, 4, 6)& realize using NAND & NOR gates.
a) Subtract FF3 - F99 using 15's & 16’s complement.

24B81A0417
a) Minimize F = Π(0, 1, 2, 3)& realize using NAND & NOR gates.
b) Subtract 100 - 001 using 9's & 10’s complement.

24B81A0418
b) Find POS for F = Π(3, 5, 7)& realize using NAND & NOR gates.
a) Subtract 212 - 121 using 9's & 10’s complement.

24B81A0419
a) Derive POS form for F = Π(0, 2, 5, 6)& realize using NAND & NOR gates.
b) Subtract 485 - 378 using 9's & 10’s complement.

24B81A0420
b) Simplify F = Π(1, 2, 3, 4)& realize using NAND & NOR gates.
a) Subtract 700 - 199 using 9's & 10’s complement.

24B81A0421
a) Simplify F(W, X, Y, Z) = Σ(0, 2, 5, 7, 8, 10)& realize using NAND & NOR gates.
b) Subtract 10111010 - 01010101 using 1's & 2’s complement.

24B81A0422
b) Find minimal SOP for F = Σ(1, 3, 9, 11, 13)& realize using NAND & NOR gates.
a) Subtract 11100000 - 01100101 using 1's & 2’s complement.

24B81A0423
a) Use K-Map: F = Σ(0, 1, 2, 8, 9)& realize using NAND & NOR gates.
b) Subtract 00011101 - 11101100 using 1's & 2’s complement.

24B81A0424
b) Derive SOP for F = Σ(3, 5, 7, 15)& realize using NAND & NOR gates.
a) Subtract 10000001 - 10000001 using 1's & 2’s complement.

24B81A0425
a) Minimize F = Σ(0, 4, 8, 12)& realize using NAND & NOR gates.
b) Subtract 01101010 - 10111011 using 1's & 2’s complement.

24B81A0426
b) Use K-Map for F = Σ(2, 3, 6, 7)& realize using NAND & NOR gates.
a) Subtract 00111000 - 00011100 using 1's & 2’s complement.

24B81A0427
a) Simplify F = Σ(0, 1, 5, 7, 13)& realize using NAND & NOR gates.
b) Subtract 11111111 - 10101010 using 1's & 2’s complement.

24B81A0428
b) Derive SOP for F = Σ(4, 5, 6, 7)& realize using NAND & NOR gates.
a) Subtract 10000000 - 01111111 using 1's & 2’s complement.

24B81A0429
a) Use K-Map: F = Σ(1, 3, 5, 7, 9)& realize using NAND & NOR gates.
b) Subtract 01000000 - 10000000 using 1's & 2’s complement.

24B81A0430
b) Simplify F = Σ(6, 7, 14, 15)& realize using NAND & NOR gates.
a) Subtract 11110000 - 11100000 using 1's & 2’s complement.

24B81A0431
a) Simplify F = Π(2, 3, 6, 7, 10)& realize using NAND & NOR gates.
b) Subtract 10110110 - 01010110 using 1's & 2’s complement.

24B81A0432
b) Minimize F = Π(0, 1, 4, 5, 8)& realize using NAND & NOR gates.
a) Subtract 11100000 - 11111111 using 1's & 2’s complement.

24B81A0433
a) Find POS for F = Π(1, 3, 5, 7)& realize using NAND & NOR gates.
b) Subtract 10000001 - 00000001 using 1's & 2’s complement.

24B81A0434
b) Derive POS form: F = Π(9, 11, 13, 15)& realize using NAND & NOR gates.
a) Subtract 01100011 - 00110011 using 1's & 2’s complement.

24B81A0435
a) Simplify F = Π(0, 2, 4, 6, 8)& realize using NAND & NOR gates.
b) Subtract 10101010 - 11111111 using 1's & 2’s complement.

24B81A0436
b) Use K-Map for F = Π(5, 6, 7, 8)& realize using NAND & NOR gates.
a) Subtract 00010001 - 00000001 using 1's & 2’s complement.

24B81A0437
a) Derive POS form: F = Π(0, 1, 2, 3)& realize using NAND & NOR gates.
b) Subtract 01010101 - 10101010 using 1's & 2’s complement.

24B81A0438
b) Minimize F = Π(8, 10, 12, 14)& realize using NAND & NOR gates.
a) Subtract 00000000 - 11111111 using 1's & 2’s complement.

24B81A0439
a) Use K-Map: F = Π(3, 6, 9, 12)& realize using NAND & NOR gates.
b) Subtract 11111111 - 00000000 using 1's & 2’s complement.

24B81A0440
b) Simplify F = Π(2, 4, 6, 8, 10)& realize using NAND & NOR gates.
a) Subtract 01010101 - 01010101 using 1’s & 2's complement

24B81A0441
a) F = Σ(1, 2, 5), d = (0, 3)& realize using NAND & NOR gates.
b) Subtract 765 - 432 using 7's & 8’s complement.

24B81A0442
b) F = Σ(0, 3, 4), d = (1, 5)& realize using NAND & NOR gates.
a) Subtract 700 - 777 using 7's & 8’s complement.

24B81A0444
a) F = Σ(2, 6), d = (0, 1, 3)& realize using NAND & NOR gates.
b) Subtract 123 - 456 using 7's & 8’s complement.

24B81A0446
b) F = Σ(4, 5), d = (2, 7)& realize using NAND & NOR gates.
a) Subtract 741 - 132 using 7's & 8’s complement.

24B81A0447
a) F = Σ(1, 3, 6), d = (0, 2)& realize using NAND & NOR gates.
b) Subtract 354 - 123 using 7's & 8’s complement.

24B81A0448
b) F = Σ(1, 5), d = (3, 4, 6)& realize using NAND & NOR gates.
a) Subtract 255 - 644 using 7's & 8’s complement.

24B81A0449
a) F = Σ(0, 4), d = (1, 5, 7)& realize using NAND & NOR gates.
b) Subtract 123 - 123 using 7's & 8’s complement.

24B81A0450
b) F = Σ(3, 5), d = (0, 2, 6)& realize using NAND & NOR gates.
a) Subtract 644 - 123 using 7's & 8’s complement.

24B81A0451
a) F = Σ(1, 7), d = (3, 4, 6)& realize using NAND & NOR gates.
b) Subtract 777 - 321 using 7's & 8’s complement.

24B81A0452
b) F = Σ(2, 6), d = (0, 1, 5)& realize using NAND & NOR gates.
a) Subtract 123 - 765 using 7's & 8’s complement.

24B81A0453
a) F = Σ(1, 3, 5, 7), d = (0, 2)& realize using NAND & NOR gates.
b) Subtract 456 - 321 using 7's & 8’s complement.

24B81A0454
b) F = Σ(4, 6, 8, 10), d = (5, 9)& realize using NAND & NOR gates.
a) Subtract 700 - 345 using 7's & 8’s complement.

24B81A0455
a) F = Σ(3, 7, 11, 15), d = (1, 2)& realize using NAND & NOR gates.
b) Subtract 654 - 321 using 7's & 8’s complement.

24B81A0456
b) F = Σ(1, 2, 8, 9), d = (0, 3, 10)& realize using NAND & NOR gates.
a) Subtract 123 - 456 using 7's & 8’s complement.

24B81A0457
a) F = Σ(0, 1, 4, 5), d = (2, 6)& realize using NAND & NOR gates.
b) Subtract 400 - 200 using 7's & 8’s complement.

24B81A0458
b) F = Σ(5, 6, 7, 13), d = (4, 12)& realize using NAND & NOR gates.
a) Subtract 777 - 777 using 7's & 8’s complement.

24B81A0459
a) F = Σ(3, 6, 9), d = (2, 10, 11)& realize using NAND & NOR gates.
b) Subtract 765 - 111 using 7's & 8’s complement.

24B81A0460
b) F = Σ(2, 5, 8), d = (0, 4, 12)& realize using NAND & NOR gates.
a) Subtract 567 - 210 using 7's & 8’s complement.

24B81A0461
a) F = Σ(1, 3, 7), d = (6, 14)& realize using NAND & NOR gates.
b) Subtract 111 - 222 using 7's & 8’s complement.

24B81A0462
b) F = Σ(0, 6, 10), d = (4, 8, 12)& realize using NAND & NOR gates.
a) Subtract 321 - 123 using 7's & 8’s complement.

24B81A0463
a) F = Σ(1, 3, 5, 7), d = (0, 2)& realize using NAND & NOR gates.
b) Subtract A2F - 3BC using 15's & 16’s complement.

24B81A0464
b) Derive SOP for F = Σ(4, 5, 6, 7)& realize using NAND & NOR gates.
a) Subtract FFF - 789 using 15's & 16’s complement.

24B81A0465
a) Use K-Map: F = Σ(1, 3, 5, 7, 9)& realize using NAND & NOR gates.
b) Subtract 456 - AAA using 15's & 16’s complement.

24B81A0466
b) Use K-Map to simplify F = Π(0, 2, 3, 7)& realize using NAND & NOR gates.
a) Subtract 999 - 111 using 15's & 16’s complement.

LE-1
a) Simplify using K-Map: F = Π(1, 4, 6)& realize using NAND & NOR gates.
b) Subtract ABC - DEF using 15's & 16’s complement.

LE-2
b) Use K-Map to simplify F = Σ(1, 2, 4, 7)& realize using NAND & NOR gates.
a) Subtract 123 - 456 using 15's & 16’s complement.

LE-3
a) Derive minimal SOP form for F = Σ(3, 5, 7)& realize using NAND & NOR gates.
b) Subtract CBA - 999 using 15's & 16’s complement.

LE-4
b) Use K-Map for F = Σ(2, 3, 6, 7)& realize using NAND & NOR gates.
a) Subtract 555 - 555 using 15's & 16’s complement.

LE-5
a) Simplify F = Σ(0, 1, 5, 7, 13)& realize using NAND & NOR gates.
b) Subtract FFE - 001 using 15's & 16’s complement.

LE-6
b) Find POS for F = Π(3, 5, 7)& realize using NAND & NOR gates.
a) Subtract AAA - BBB using 15’s & 16'scomplement.

LE-7
a) Find sop for F = Π(3, 5,6 7)& realize using NAND & NOR gates.
b) Subtract A9A - D07 using 15’s & 16'scomplement.

Saturday, July 12, 2025

STLD: UNIT-1

UNIT-1:
click here for Kmap practice questions

L1:Representation of numbers of different radix, conversion from one radix to another radix                                                                                                                              Click Here For   Video Lecture 1

L2:NUMBER CONVERSION, DECIMAL, OCTAL ,HEXADECIMAL, BINARY AND VICEVERSA                                                                                                                Click Here For   Video Lecture 2

L3:NUMBER CONVERSION AND INTRODUCTION TO COMPLIMENTS, 1'S AND 2'S COMPLIMENTS                                                                            Click Here For   Video Lecture 3  

L4:SUBTRACTION USING r's COMPLIMENTS, SUBTRACTION USING (r-1)'s COMPLIMENTS
                                                                                                        Click Here For   Video Lecture 4

L5:DECIMAL SUBTRACTION, BINARY SUBTRACTION, HEXADECIMAL SUBTRACTION
                                                                                                        Click Here For   Video Lecture 5

L6: BINARY CODES,8421,2421,84-2-1,EX-3,GRAYCODE
                                                                                                        Click Here For   Video Lecture 6


L7:ERROR DETECTING & CORRECTING CODES , HAMMING CODE

L8:LOGIC GATES, 2 I/P LOGIC GATES & 3 I/P LOGIC GATES
                                                                                                        Click Here For   Video Lecture 8

L9: LOGIC GATES IC 7400,IC 7402,IC 7404, IC 7408, IC 7486, IC 7432, IC 7410, IC 7420, IC 74266.
BOOLEAN ALGEBRA, BOOLEAN LAW, OR LAW, IDENTITY LAW, IDEMPOTENCE LAW
                                                                                                        Click Here For   Video Lecture 9

L10: BOOLEAN LAWS & THEOREMS
BOOLEAN LAWS & THEOREMS, DISTRIBUTIVE LAW, ABSORPTION LAW, SIMPLIFICATION THEOREM, TRANSPORTATION LAW, CONSENSUS THEOREM, DEMORGAN LAW
                                                                                                       Click Here For   Video Lecture 10

L11: REALISATION SOP AND POS USING UNIVERSAL GATES
                                                                                        Click Here For   Video Lecture 11

L12:  SIMPLIFICATION OF BOOLEAN EXPRESSION
                                                                                        Click Here For   Video Lecture 12


L13:SOP,POS,STANDARD SOP,STANDARD POS, MIN TERMS,MAXTREMS
                                                                                                      Click Here For   Video Lecture 13
L14: CANONICAL SOP & CANONICAL POS PROBLEMS 
                                                                                                    Click Here For   Video Lecture 14
L15: PROBLEM ON BOOLEAN ALGEBRA
                                                                                                    Click Here For   Video Lecture 15


https://ecelegend.blogspot.com/2025/07/k-map-practice-questions.html
every one must complete work 

STLD OBJECTIVE QUESTION 1

 STLD MID I MCQ  UNIT-I: Review of Number Systems & Codes & Boolean Algebra & Logic Operations 1What is the radix of the hexa de...