UNIT -1
1. ________ symbol identifies a system task. [ ]
(a) / (b) $
(c) # (d) %
2. The higher level of design description next to circuit level is __________ level. [ ]
(a) Switch level (b) Gate level
(c) Data flow level (d) Behavioural level.
3. Any program written to test a design description is, [ ]
(a) Module (b) Stimulus module
(c) Test bench (d) All of the above
4. Functions are used in all programming languages is known as [ ]
(a) Subroutines (b) Level
(c) Programs (d) Languages
5. In verilog, the system task used for controlling system is [ ]
(a) $ display (b) $ monitor
(c) $ finish (d) All of the above
6. The two groups of data types are, [ ]
(a) Variable and et data type (b) Wire and tri-data type
(c) Integer (d) Real
7. The two types of numbers used in verilog are [ ]
(a) Decimal and real (b) Integer and real
(c) Base form and real (d) None of the above
8. In order to increase readability of a digital design, __________ are written in a verilog code. [ ]
(a) Programs (b) Functions
(c) Operands (d) Comments
9. White space characters are used to separate [ ]
(a) Numbers (b) Keywords
(c) Identifiers (d) Integers
10. When a string of ASCII characters are used as an operand in an expression, it is treated as, [ ]
(a) Real number (b) Octal number
(c) Binary number (d) None of the above
K E Y
1. (b) 2. (b) 3. (d) 4. (a) 5. (c)
6. (a) 7. (b) 8. (d) 9. (b) 10. (c)
OBJECTIVE TYPE
UNIT - 2
1. Multiplexers are also known as, [ ]
(a) Data finder (b) Data deselectors
(c) Data selector (d) None of the above
2. The ripple carry adder requires a significant amount of time to complete the addition step,
and the time delay experienced during the process is referred to as _____ (or) _____. [ ]
(a) Carry propagation delay (b) Inter-stage carry delay
(c) Both a & b (d) None
3. To overcome this limitation of ripple carry adder and accelerate the addition process, a new technique
called _________ is implemented. [ ]
(a) Look ahead-carry addition (b) Carry addition
(c) BCD adder (d) Multiplexer
4. The problem of subtraction is changed into a problem of addition by using _____ representations. [ ]
(a) 10’s complement (b) Adder
(c) 9’s complement (d) 1’s and 2’s complement
5. An 8:1 multiplexer is available in the form of _____ & _____ IC’s. [ ]
(a) 74157 & 74158 (b) 74151 & 74152
(c) 74151 & 74157 (d) None
6. IC 74181 is used as _____. [ ]
(a) ALU (b) comparator
(c) Adder (d) Subtractor
7. 74 × 85 IC is a _____ bit MSI comparator and to design a 16-bit comparator _____ number
of 74 × 85 comparators has to be cascaded. [ ]
(a) 4-bit, 5 (b) 16-bit, 1
(c) 4-bit, 4 (d) 8-bit, 4
8. The 74180 has dual functions; it can be used as a _____ as well as a _____. [ ]
(a) Parity generator, Priority encoder (b) Parity checker, Priority encoder
(c) Parity generator, Parity checker (d) None
9. In BCD-to-binary converter using IC 74185A, the _____ of the binary input skips (bypasses)
the converter and appears as the _____of BCD output.
(a) LSB, LSB (b) LSB,MSB
(c) MSB,LSB (d) MSB,MSB
10. An IC 74148 is used as _____ [ ]
(a) Octal-to-Binary Priority Encoder (b) Decimal-to-BCD Priority Encoder
(c) BCD-to-Binary Converter (d) None
11. Which of the following is not an arthmetic circuit? [ ]
(a) 4 - bit comparator (b) 16 - bit BCD adder
(c) Ripple carry adder (d) BCD to 7 segment code converter
K E Y
1. (c) 2. (a) 3. (d) 4. (b) 5. (a)
6. (c) 7. (c) 8. (a) 9. (a) 10. (a)
11. (d)
UNIT - 3
1. Parallel access shift register performs, [ ]
(a) Parallel to serial conversion
(b) Serial to parallel conversion
(c) Parallel to parallel conversion
(d) Both (a) and (b)
2. ______ counter counts only in one direction (i.e., either up or down). [ ]
(a) Up-down counter
(b) Single mode counter
(c) Multi mode counter
(d) None of the above
3. A 4-bit ring counter is also known as, [ ]
(a) Universal register
(b) Parallel register
(c) Circular shift register
(d) None of the above
4. LFSR is also known as [ ]
(a) Maximum length sequence generator
(b) Minimum length sequence generator
(c) Shift circular register
(d) Johnson counter
5. Moebius counter is also called as [ ]
(a) Ring counter
(b) Twisted-ring counter
(c) Johnson counter
(d) Both (b) and (c)
6. The glitch free outputs are present in ____________ counter. [ ]
(a) Johnson
(b) Ring
(c) Twisted-ring
(d) None
7. 74 × 163 is a synchronous 4-bit binary ____________ counter with active-low load and clear inputs [ ]
(a) MSI
(b) Ring
(c) Johnson
(d) None
8. Specialized ____________ functions are used for data encryption and decryption. [ ]
(a) Combinational
(b) Arithmatic
(c) Sequential
(d) None
9. In sequential circuits, output depends on, [ ]
(a) Present input and future output
(b) Present input and output
(c) Present input and past output
(d) Present input only
10. Which of the following are true about sequential circuits? [ ]
(a) Input signals can effect memory elements
(b) Circuits are simple to design
(c) Speed of operation is limited
(d) All of the above
11. Asynchronous sequential circuits use , [ ]
(a) Timer delay latches
(b) Gate devices
(c) Memory elements
(d) All of the above
12. ________ is a pictorial representation of the behavior of a sequential circuit. [ ]
(a) State table
(b) State diagram
(c) State assignment
(d) Flow table
13. _______ is the next portion of state table. [ ]
(a) Tabular
(b) Flow table
(c) Transition
(d) State diagram
14. Which of the following are the major fundamentals for VHDL [ ]
(a) Library support
(b) Timing control
(c) Concurrency
(d) All of the above
15. _________ provides the interface between the device and other external peripherals. [ ]
(a) Entity declaration
(b) Package body
(c) Architecture
(d) Package declaration
16. _____ is used for a unidirectional ouput signal. [ ]
(a) in
(b) Buffer
(c) Out
(d) inout
17. The common package declarations can be shared by many design units by using [ ]
(a) Library clause
(b) Use clause
(c) Both (a) and (b)
(d) None of the above
18. Process is used to declare, [ ]
(a) Variables
(b) Constants
(c) Functions
(d) All of the above
19. In __________ description, the circuits are represented interms of flow of data and elements. [ ]
(a) Behavioral
(b) Structural
(c) Data flow
(d) Both (b) and (c)
20. In component declaration, every individual component is declared with unique [ ]
(a) Name-identifier
(b) Number
(c) Type of the input and output ports
(d) All of the above
21. In _____ type, data elements are represented in a sequential manner [ ]
(a) Scalar
(b) Composite
(c) Access
(d) File
22. ______ data type indicates the files that are present in host environment. [ ]
(a) Access
(b) Composite
(c) File
(d) Scalar
23. Which of the following are the example of a signal object? [ ]
(a) Signal CLOCK:BIT;
(b) signal DATABUS:BIT VECTOR (0 to 15);
(c) Both (a) and (b)
(d) type BIT_FILE
24. Which of the following is true about basic identifier? [ ]
(a) Character must begin with a letter but, should not end with an underscore
(b) Character cna be both upper case and lower case letter
(c) It should not contain two underscore characters.
(d) All of the above
25. A library consists of [ ]
(a) Shared Designs
(b) Shared implementations
(c) Shared declarations
(d) All of the above
26. STD library includes, [ ]
(a) Basic definitions
(b) Type of VHDL language
(c) Utilities for text
(d) Both (a) and (b)
27. In IEEE.STD_LOGIC_1164.ALL ; ALLmeans, [ ]
(a) Use all definitions of file
(b) Use all variables of file
(c) Use all constants of file
(d) All of the abpve.
28. The process of associating a design entity and an architecture to a component instance is known as, [ ]
(a) Binding
(b) Component installation
(c) Component declaration
(d) Package declaration
29. Which of the statements are used to stoop the execution? [ ]
(a) Process
(b) Wait
(c) Variable assignment
(d) Signal assignment
30. Wait for ‘0‘ns indicates the processor to wait for, [ ]
(a) ‘0‘ns
(b) Less than ‘0‘ns
(c) One data cycle
(d) None of the above
31. In ______ loop, the statements are repeated until a specified condition becomes false. [ ]
(a) While
(b) Simple
(c) For
(d) All of the above
32. _______ statement is used inside the loop to terminate statements unconditionally. [ ]
(a) Next
(b) Assertion
(c) Terminate
(d) Exit
33. Which of the following is used to eliminate unwanted splices and transients in signals. [ ]
(a) Transport delay
(b) Insertion delay
(c) Delta delay
(d) Both (b) and (c)
34. In the syntax, Target_Signal<=transport A after trasnport_delay; represents, [ ]
(a) Input
(b) Output
(c) Transport delay value
(d) Input-Output value
35. The process of automatic transformation of higher level abstraction to a lower level abstraction
is known as. [ ]
(a) Synthesis
(b) Translation
(c) Minimization
(d) Optimization
36. Which of the following are the functions of logic synthesizer? [ ]
(a) Translation
(b) Logic minimization and Optimization
(c) Mapping to gates
(d) All of the above
37. Translation operation is performed using , [ ]
(a) AND, OR gates
(b) Flip flops
(c) Latches
(d) All of the above
38. Logic optimization uses___ to make the equations of synthesizer network. [ ]
(a) Sequence of factoring
(b) Substitution operation
(c) Elimination operation
(d) All of the above
K E Y
1. (d) 2. (b) 3. (c) 4. (a) 5. (d)
6. (b) 7. (a) 8. (c) 9. (b) 10. (d)
11. (d) 12. (b) 13. (a) 14. (d) 15. (a)
16. (b) 17. (c) 18. (a) 19. (c) 20. (d)
21. (a) 22. (c) 23. (c) 24. (d) 25. (d)
26. (a) 27. (a) 28. (a) 29. (b) 30. (a)
31. (a) 32. (d) 33. (b) 34. (d) 35. (a)
36. (d) 37. (d) 38. (d)
