STLD SHORT QUESTION

 WRITE THE SOLUTION FOR THESE QUESTION AND SUBMIT BEFORE LAB INTERNAL EXAMS. THESE QUESTIONS WILL BE ASKED FOR VIVA VOCE

FINATE STATE MACHINES

 

Finite State Machines are the fundamental building blocks of various digital and computing systems. They provide a systematic approach to model the behavior of sequential circuits. They also help to control various processes in digital systems.

Read this chapter to learn the components, types, advantages, and applications of finite state machines.

What is a Finite State Machine?

A Finite State Machine (FSM) is a mathematical model that is used to explain and understand the behavior of a digital  system. More specifically, it is a structured and systematic model that helps to understand the behavior of a sequential circuit that exists in a finite number of states at a given point of time.

In more simple words, a synchronous sequential circuit is also called as Finite State Machine FSM, if it has a finite number of states.

The transition of these finite states takes place based on the internal or external inputs that results in the predictable and systematic changes in the behavior of the system.

Components of a Finite State Machine

A typical finite state machine consists of the following main components −

Finite States

The finite states are nothing but the distinct modes or conditions in the given system. Each of these finite states represents a specific behavior. In digital system representation, these finite states are generally represented through symbols or labels.

States represent the different conditions or situations in which the system can exist. Each state defines a specific behavior of the system. The FSM can be in only one state at a time, and the total number of states is finite. States are represented as circles in diagrams and stored in memory elements (flip-flops). Example: Red, Yellow, Green lights in a traffic controller.

State Transitions

In terms of finite state machines, the state transition can be defined as the change from one state to another. This change in state or state transition takes placed based on some specific inputs or conditions. These state transitions are generally triggered by events which are associated with some rules or conditions and determine the next state of the system.

A state transition is the change from one state to another based on input conditions. These transitions are shown by directed arrows in the state diagram. Each arrow is labeled with input/output values depending on the FSM type (Mealy or Moore). Example: If input=1, the machine moves from state A to B; if input=0, it remains in A.

State Diagram

The state transition and the behavior of a finite state machine can be represented in a graphical form that is known as state diagram of the finite state machine.

Inputs

The inputs to the finite state machines are the external signals that trigger the state transitions in the system. These inputs are to be entered into the finite state machine by using sensors, user input devices like mic, keyboard, etc.

Inputs are external signals that control the state transitions of the FSM. They decide which next state the FSM should move to. Inputs can come from sensors, switches, or other circuits. Example: In an elevator, inputs are floor buttons or door sensors. 

Outputs

The results produced by the system as per the inputs and current states are known as outputs. These outputs of the system can be used to trigger events, control actuators, or to provide feedback to the external environment.

Outputs are the responses produced by the FSM based on its current state and inputs. Outputs may drive actuators, LEDs, or control signals. In Mealy machines, outputs depend on state + input; in Moore machines, outputs depend only on state. Example: A vending machine outputs 'dispense item' when correct coins are inserted.

In digital hardware, FSMs also include the following supporting components: Memory Elements (Flip-Flops): Store the current state of the FSM and update at each clock pulse. Combinational Logic: Generates next state and output based on current state and input. Clock Signal: Synchronizes state transitions at each clock edge. Reset Signal: Initializes the FSM to a known starting state when powered on

Types of Finite State Machine

There are two types of finite state machines namely,

• Mealy State Machine
• Moore State Machine

Let us now discuss these two types of finite state machines in detail.

Mealy State Machine

A Finite State Machine is said to be a Mealy state machine, if its outputs depend on both present inputs & present states. The block diagram of the Mealy state machine is shown in the following figure −

As shown in the figure, there are two main parts presents in the Mealy state machine. Those are combinational logic circuit and memory element. The memory element is useful to provide some part of previous outputs and present states as inputs to the combinational logic circuit.

Based on the present inputs and present states, the Mealy state machine produces outputs. Therefore, the outputs will be valid only at positive or negative transition of the clock signal.

State Diagram of Mealy State Machine

The state diagram of Mealy state machine is shown in the following figure.

In the above figure, there are three states, namely A, B and C. These states are labelled inside the circles and each circle corresponds to one state. State transitions between these states are represented with directed lines. Here, 0 / 0, 1 / 0 and 1 / 1 denote the input / output. In the above figure, there are two state transitions from each state based on the value of input.

In general, the number of states required in Mealy state machine is less than or equal to the number of states required in Moore state machine. There is an equivalent Moore state machine for each Mealy state machine.

Moore State Machine

A Finite State Machine is said to be a Moore state machine, if its outputs depend only on the present states.

The block diagram of the Moore state machine is shown in the following figure −

As shown in above figure, there are two parts presents in a Moore state machine. Those are combinational logic and memory. In this case, the present inputs and present states determine the next states. So, based on next states, Moore state machine produces the outputs. Therefore, the outputs will be valid only after transition of the state.

State Diagram of Moore State Machine

The state diagram of Moore state machine is shown in the following figure −

In the above figure, there are four states, namely A, B, C, and D. These states and the respective outputs are labelled inside the circles. Here, only the input value is labeled on each transition. In the above figure, there are two transitions from each state based on the value of input.

In general, the number of states required in Moore state machine is more than or equal to the number of states required in Mealy state machine. There is an equivalent Mealy state machine for each Moore state machine. So, based on the requirement we can use one of them.

Advantages of Finite State Machine

The Finite State Machines have several advantages in the field of digital electronics. All these advantages make them a crucial tool for modeling and implementing various digital systems. Some key advantages of Finite State Machines are listed below −

• Finite state machines provide a simple and systematic way to model and understand the behavior of digital systems with discrete finite states and transitions between them.
• Finite state machines support modular designs that help to breakdown the complex digital systems into smaller components. Each component of the finite state machine can represent a specific task of the entire system. This allows for easier design, testing, and maintenance.
• Finite state machines provide ease in terms of scalability that allows for addition of new states and transitions, and logics to the existing system without altering its fundamental structure or operation. This becomes essential when the system requirement evolve or expand.
• Fundamentally, finite state machines have a deterministic or predictable behavior. That means, we can easily determine the next state of the system from its current state and the inputs. This predictable behavior helps us to ensure the reliable and consistent operation of the system. It also makes the finite state machines best suited for real-time and safety-critical applications.
• Finite state machines are considered highly efficient in terms of both hardware and software implementations, as they require minimal hardware and software resources such as logic gates, memory, and other processing resources.
• Finite state machines support parallelism. This technology allows the occurrence of multiple states and state transitions simultaneously within the system. It also optimizes the performance and improves the responsiveness of the system.
• Finite state machines are versatile tools in the field of digital electronics and computer science, as they find their applications in various fields such as digital system design, control system design, software development, development of artificial intelligence, etc.

Applications of Finite State Machine

In the field of digital electronics and computer science, the finite state machines are used in various applications due to their ability to model sequential logic systems effectively. Here are some examples of applications of finite state machines −

• Finite state machines are commonly used in designing and implementation of different types of sequential logic circuits, such as digital counters, timers, control units, etc.
• Finite state machines are used in digital control systems to control and regulate the behavior of complex automated systems, like robots, industrial control and automation systems, etc.
• Finite state machines are used in the implementation of communication protocols like network protocols and state-based digital systems like data transmission and protocol converters.
• Finite state machines are also used in the field of software development to model and define the behavior of state-based systems in applications, to create user interfaces, to implement game mechanics, and to develop workflow management systems.

STLD OBJECTIVE QUESTION 1

 STLD MID I MCQ 

UNIT-I: Review of Number Systems & Codes & Boolean Algebra & Logic Operations

1What is the radix of the hexa decimal number system?

a) 2 b) 8 c) 10 d) 16

Answer: d) 16

2Which code represents each decimal digit with a 4-bit binary code?

a) Gray code b) Excess-3 code c) BCD code d) 2421 code

Answer: c) BCD code

3How is Gray code different from binary code?

a) It uses more bits. b) Adjacent code values differ by only one bit.

c) It is a weighted code. d) It is primarily used for error detection.

Answer: b) Adjacent code values differ by only one bit.

4Which type of parity checking adds a bit to make the total number of 1s even?

a) Odd parity b) Even parity c) Hamming code d) Cyclic Redundancy Check

Answer: b) Even parity

5What is the purpose of Hamming code?

a) Error detection only b) Error correction only 

c) Error detection and correction d) Data compression

Answer: c) Error detection and correction

6Which Boolean theorem states that A+(B+C)=(A+B)+C

a) Commutative Law b) Associative Law c) Distributive Law d) De Morgan's Theorem

Answer: b) Associative Law

7The principle of duality in Boolean algebra involves interchanging which operations and constants?

a) AND and OR, 0s and 1s b) NOT and XOR, As and A's

c) NAND and NOR, inputs and outputs d) SOP and POS forms

Answer: a) AND and OR, 0s and 1s

8According to De Morgan's theorem, (A⋅B)′is equivalent to:

a) A′+B′ b) A′⋅B′ c) A+B d) A⋅B

Answer: a) 𝐴′+𝐵′

9Which of the following is considered a universal logic operation?

a) OR b) AND c) NOT d) NAND

Answer: d) NAND

10What is the standard form that represents a Boolean expression as a sum of product terms?

a) POS b) SOP c) NAND-NAND d) NOR-NOR

Answer: b) SOP

11What is the 1's complement of the binary number 10110?

a) 01001 b) 01010 c) 10101 d) 11001

Answer: a) 01001

12What is the 2's complement of the binary number 10110?

a) 01001 b) 01010 c) 10101 d) 11001

Answer: b) 01010

13The Excess-3 code for decimal digit 5 is:

a) 0101 b) 1000 c) 0010 d) 1011

Answer: b) 1000

14How many bits are required to represent a hexadecimal digit?

a) 2 b) 3 c) 4 d) 8

Answer: c) 4

15If a binary number is converted to Gray code, how many bits differ between adjacent code words?

a) All bits b) Two bits c) One bit d) Zero bits

Answer: c) One bit

16Which code is a self-complementing BCD code?

a) 8421 code b) Gray code c) Excess-3 code d) 2421 code

Answer: c) Excess-3 code

17The expression for De Morgan's theorem for OR operation is:

a) (𝐴+𝐵)′=𝐴′⋅𝐵′ b) (𝐴⋅𝐵)′=𝐴′+𝐵′ c) 𝐴+𝐵=𝐵+𝐴 d) 𝐴⋅(𝐵+𝐶)=𝐴⋅𝐵+𝐴⋅𝐶

Answer: a) (𝐴+𝐵)′=𝐴′⋅𝐵′

18Which logic gate outputs a HIGH only when all inputs are HIGH?

a) OR b) NOR c) AND d) XOR

Answer: c) AND

19Which logic gate is obtained by inverting the output of an OR gate?

a) AND b) NAND c) NOR d) XOR

Answer: c) NOR

20What is the main advantage of using NAND-NAND and NOR-NOR realizations?

a) Reduced complexity of circuits b) Easier to implement universal gates

c) Reduced power consumption d) Fewer gates required compared to other realizations

Answer: d) Fewer gates required compared to other realizations

UNIT-II: Minimization Techniques & Combinational Logic Circuits Design

1What is the maximum number of variables a K-Map can efficiently minimize according to the text?

a) 4 b) 5 c) 6 d) 8

Answer: c) 6

2The Quine-McCluskey method is also known as the:

a) Graphical method b) Tabular method

c) Boolean algebra method d) Karnaugh map method

Answer: b) Tabular method

3A Half Adder circuit is used to add:

a) Three binary bits b) Two binary bits

c) Four binary bits d) Multiple binary numbers

Answer: b) Two binary bits

4How many inputs does a Full Adder take?

a) One b) Two c) Three d) Four

Answer: c) Three

5Which circuit is used to find the difference between two single binary digits?

a) Full Adder b) Half Subtractor c) Full Subtractor d) BCD Adder

Answer: b) Half Subtractor

6 A 4-bit adder-subtractor circuit can perform:

a) Only addition b) Only subtraction c) Both addition and subtraction d) Multiplication

Answer: c) Both addition and subtraction

7 What is the primary advantage of a carry look-ahead adder?

a) Reduces power consumption b) Increases propagation delay

c) Reduces propagation delay d) Simplifies circuit design

Answer: c) Reduces propagation delay

8 In K-map minimization, a group of 8 adjacent 1s eliminates how many variables?

a) 1 b) 2 c) 3 d) 4

Answer: c) 3

9 The Quine-McCluskey method is particularly useful for minimizing Boolean functions with:

a) Few variables b) Many variables c) Only two variables d) Only one output

Answer: b) Many variables

10 Which combinational circuit is used to add two BCD numbers?

a) Full Adder b) Ripple Carry Adder c) BCD Adder d) Excess-3 Adder

Answer: c) BCD Adder

11 How many inputs does a Half Subtractor have?

a) 1 b) 2 c) 3 d) 4

Answer: b) 2

12 What is the output of a Half Subtractor?

a) Sum and Carry b) Difference and Borrow

c) Sum and Difference d) Carry and Borrow

Answer: b) Difference and Borrow

13 Which circuit is a modified BCD adder that works with Excess-3 code inputs?

a) Ripple Carry Adder b) Carry Look-Ahead Adder

c) Excess-3 Adder d) Parallel Adder

Answer: c) Excess-3 Adder

14To realize a three-level logic circuit, which forms can be used?

a) Only SOP b) Only POS c) NAND-NAND or NOR-NOR d) Universal gates only

Answer: c) NAND-NAND or NOR-NOR

15 The main goal of minimization techniques in digital logic is to:

a) Increase circuit complexity b) Reduce the number of gates

c) Increase propagation delay d) Use more components

Answer: b) Reduce the number of gates

16 Which method is suitable for minimizing switching functions with up to 6 variables?

a) Quine-McCluskey method b) K-Map

c) Boolean theorems only d) Tabular method only

Answer: b) K-Map

17 What is the sum output of a Half Adder with inputs A and B?

a) 𝐴⋅𝐵 b) 𝐴+𝐵 c) 𝐴⊕𝐵 d) 𝐴′+𝐵′

Answer: c) 𝐴⊕𝐵

18 The carry output of a Half Adder with inputs A and B is:

a) 𝐴⋅𝐵 b) 𝐴+𝐵 c) 𝐴⊕𝐵 d) 𝐴′+𝐵′

Answer: a) 𝐴⋅𝐵

19 The design of a 4-bit adder-subtractor circuit relies on using:

a) Half Adders b) Full Subtractors c) Full Adders d) Universal gates

Answer: c) Full Adders

20 What is the primary characteristic of a combinational logic circuit?

a) Output depends on present and past inputs b) Contains memory elements

c) Output depends only on present inputs d) Used for sequential operations

Answer: c) Output depends only on present inputs

critical thinking practice problems

GROUP -A

1. Smart Elevator Control Logic

A smart elevator controller has 4 binary sensors:

• F: Floor requested (0 = even floor, 1 = odd floor)

• O: Overload sensor (0 = not overloaded, 1 = overloaded)

• D: Door open (0 = closed, 1 = open)

• E: Emergency button (0 = normal, 1 = emergency)

The elevator should start moving (output = 1) only under the following rules:

• It is not overloaded, and

• The door is closed, and

• Either:

  • A valid floor request is made, or

  • Emergency mode is activated

Frame the minimized logic expression that controls movement.

---

🔹 2. Industrial Fan Safety System

In a chemical plant, a fan must be automatically turned ON when dangerous conditions arise.
Inputs:

• T = 1 if Temperature > 70°C

• G = 1 if Gas leakage is detected

• P = 1 if Power is available

• M = 1 if Manual override is enabled

The fan should turn on if:

• Either T or G is high, and P is available,

• Or if the manual override (M) is used (regardless of other inputs).

Design the minimized Boolean function to control the fan operation.

---

🔹 3. Smart Traffic Light Control (4-Way Intersection)

Sensors detect traffic at four roads (A, B, C, D) entering a junction.
Each sensor = 1 if traffic is detected, 0 otherwise.

A special green signal is triggered only if:

• At least three roads have traffic, and

• Road D has no traffic (priority to other directions).

Determine the minimal logic expression to control this special green signal.

---

🔹 4. Smart Irrigation Controller

Inputs:

• M = Moisture level low (1 = dry)

• R = Rain sensor (1 = rain)

• T = Timer condition met (1 = scheduled time)

• O = Operator override (1 = force on)

The irrigation pump must turn ON when:

• Moisture is low AND it is scheduled time,

• But NOT if rain is detected,

• Unless overridden by the operator.

Design and minimize the logic for the Pump ON signal.

---

🔹 5. Secure Access System – Restricted Logic

A door lock uses a 4-bit input (A, B, C, D) from a keypad. Only the following binary codes are valid to unlock the door:
0001, 0100, 1010, 1100, 1110, 1111
Other codes do not unlock the door.
Design the simplest logic function that outputs 1 for valid unlock attempts.
Also, use don't care conditions for 0000 and 1000, which are never generated.

---

🔹 6. Medical Device Alarm Logic

Inputs from sensors in a patient-monitoring device:

• H = Heart rate abnormal

• B = Blood pressure abnormal

• T = Temperature abnormal

• S = Sleep mode enabled

An alarm should activate only when:

• Any two or more vitals are abnormal, and

• Sleep mode is not enabled.

Write the Boolean function and minimize it to reduce logic hardware.

---

🔹 7. Data Transmission Fault Detection

A 4-bit checksum monitor system detects a fault when:

• The XOR of all bits is 1 (odd parity), and

• At least one bit is 1 (to ignore all-zero idle line)

Input bits: A, B, C, D
Design the logic for the Fault flag, and simplify the expression using grouping techniques.

---

 

GROUP -B

1. Complex Input Combinations (4 variables):

A digital security system uses four binary inputs A, B, C, and D. The output alarm is triggered (i.e., output = 1) for the following input states:
0, 2, 3, 6, 7, 8, 10, 11, 12, 13 (decimal values).
Additionally, the system designer notes that inputs 1 and 9 can never occur in practice.
Derive the most efficient logic expression to activate the alarm.

---

2. POS-type Minimization – Implied:

A logic function is 0 (false) for the input decimal values:
0, 1, 2, 5, 8, 9, 10, 14
For all other inputs (3, 4, 6, 7, 11, 12, 13, 15), the output is 1.
Find the minimized logic expression that defines this behavior.

---

3. Mixed Minterms with Don’t Care:

In a certain controller design, the output is 1 for the following binary combinations (decimal):
1, 3, 7, 11, 15
The combinations 0, 2, 5, 13 are considered irrelevant and may take either 0 or 1 (don’t care).
Find the most compact logic equation representing this output behavior.

---

4. Gray Code Sensitive System:

A system activates an output when the Gray code of a 3-bit input is one of the following:
000, 001, 011, 010 (in binary)
Determine the minimized Boolean expression for this output condition, using inputs A, B, and C where A is the MSB.

---

5. Pattern Recognition Function:

Design a logic function F(A, B, C, D) such that it outputs 1 only when the binary input represents a prime number less than 16 (i.e., 2, 3, 5, 7, 11, 13).
Derive the minimized Boolean expression to implement this logic.

---

6. Parity Detection with Conditions:

You have a 4-bit input (W, X, Y, Z).
The output should be 1 if the number of 1s in the input is odd, but only when W = 1.
Minimize the logic expression accordingly.

---

7. Unusual Grouped Logic Activation:

A logic circuit outputs high for inputs with the decimal values:
0, 1, 5, 7, 9, 11, 13, 15
Find the most efficient Boolean expression to represent this function.
Note: Direct SOP writing leads to long expressions; simplify optimally.

---

8. Dual Output Function Design:

Design two output functions F1 and F2 from 4 inputs A, B, C, D such that:

• F1 = 1 for minterms {0, 2, 5, 6, 8, 10, 13}

• F2 = 1 for maxterms {1, 4, 7, 9, 12, 14, 15}
  Find minimal Boolean expressions for both functions, using any valid technique.

GROUP -C

1.

A digital circuit has three inputs A, B, and C. The output F is high (1) for the following input combinations:

• A=0, B=0, C=0

• A=0, B=1, C=0

• A=1, B=0, C=0

• A=1, B=1, C=0

Minimize the Boolean expression for F using a systematic approach.

---

2.

A function F(A, B, C) is true for input combinations corresponding to the decimal values 1, 3, 5, and 7.
Determine the simplest Boolean expression for F.

---

3.

A certain logic function outputs 1 for the binary inputs:

• 0001

• 0011

• 0111

• 1111

Assume the inputs are D, C, B, A (in that order). Derive the minimized expression for the output function.

---

4.

A circuit takes four inputs W, X, Y, Z and gives output 1 only for the decimal inputs 0, 2, 5, 7, 8, 10, 13, and 15.
Find the minimized Boolean expression for the output function.

---

5.

A digital system defines an output function that is high when the input is in the set {4, 5, 6, 7, 12, 13, 14, 15} and low otherwise.
Find the most simplified expression for this output.

---

6.

Given a truth table with inputs A, B, C, D, the output is 1 for the minterms:
(1, 3, 7, 11, 15).
Simplify the Boolean function using grouping techniques.

---

7.

A certain digital logic circuit uses three inputs A, B, and C. The output is high for all input combinations where the number of 1s in the input is even (including zero).
Determine the minimal logic expression for this output.

---

8.

A control signal is active (1) when the inputs (A, B, C, D) match the binary representations of the decimal values 2, 3, 6, 7, 10, 11, 14, 15.
Write the minimized Boolean expression for this control signal.

STLD UNIT 2

 

L16: K-MAP INTRODUCTION 2, 3 VARIABLE

                                                                                                      Click Here For   Video Lecture 16

L17: KMAP 3 VARIABLES, KMAP 4 VARIABLES, EXAMPLE PROBLEMS ON KMAP 3,4 VARIABLES

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L18:K MAP 4 VARIABLE WITH DONT CARE CONDITIONS(X)

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L19:5 VARIABLE KMAP WITH POS AND SOP MINIMIZATION

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L20:MINIMIZATION AND REALIZATION

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Subtractions & K Map Practice questions

 All  the students are informed complete the assignment for K MAP both in POS & SOP, realize using NAND & NOR gates

24B81A0401

a) Simplify F(A, B, C) = Σ(0, 2, 4, 6) realize using NAND & NOR gates

b) Subtract 245 - 123 using 9's & 10’s complement.

24B81A0402

b)Find the minimized SOP expression for 

    F = Σ(1, 3, 5) & realize using NAND & NOR gates.    

a) Subtract 370 - 198 using 9's & 10’s complement.

24B81A0403

a) Use K-Map to simplify F = Σ(0, 1, 2, 3)& realize using NAND & NOR gates.

b) Subtract 120 - 389 using 9's & 10’s complement.

24B81A0404

b) Derive minimal expression for F = Σ(2, 3, 6)& realize using NAND & NOR gates.

a) Subtract 684 - 159 using 9's & 10’s complement.

24B81A0405

a) Find SOP form for F = Σ(0, 4, 5, 6)& realize using NAND & NOR gates.

b) Subtract 200 - 450 using 9's & 10’s complement.

24B81A0406

b) Simplify F = Σ(0, 1, 4)& realize using NAND & NOR gates.

a) Subtract 999 - 321 using 9's & 10’s complement.

24B81A0407

a) Use K-Map to simplify F = Σ(1, 2, 4, 7)& realize using NAND & NOR gates.

b) Subtract 805 - 607 using 9's & 10’s complement.

24B81A0408

b) Derive minimal SOP form for F = Σ(3, 5, 7)& realize using NAND & NOR gates.

a) Subtract 431 - 431 using 9's & 10’s complement.

24B81A0409

a) Find simplified function for F = Σ(0, 1, 5, 6)& realize using NAND & NOR gates.

b) Subtract 300 - 150 using 9's & 10’s complement.

24B81A0410

b) Use K-Map to simplify F = Σ(2, 3, 4, 5)& realize using NAND & NOR gates.

a) Subtract 111 - 777 using 9's & 10’s complement.

24B81A0411

a) Simplify F(A, B, C) = Π(1, 3, 5)& realize using NAND & NOR gates.

b) Subtract 236 - 142 using 9's & 10’s complement.

24B81A0412

b) Minimize F = Π(0, 2, 4, 6)& realize using NAND & NOR gates.

a) Subtract 415 - 215 using 9's & 10’s complement.

24B81A0413

a) Derive POS form for F = Π(2, 3, 6)& realize using NAND & NOR gates.

b) Subtract 150 - 389 using 9's & 10’s complement.

24B81A0414

b) Simplify F = Π(0, 4, 5, 6)& realize using NAND & NOR gates.

a) Subtract 822 - 313 using 9's & 10’s complement.

24B81A0415

a) Use K-Map to simplify F = Π(0, 2, 3, 7)& realize using NAND & NOR gates.

b) Subtract 290 - 190 using 9's & 10’s complement.

24B81A0416

b) Simplify using K-Map: F = Π(1, 4, 6)& realize using NAND & NOR gates.

a) Subtract FF3 - F99 using 15's & 16’s complement.

24B81A0417

a) Minimize F = Π(0, 1, 2, 3)& realize using NAND & NOR gates.

b) Subtract 100 - 001 using 9's & 10’s complement.

24B81A0418

b) Find POS for F = Π(3, 5, 7)& realize using NAND & NOR gates.

a) Subtract 212 - 121 using 9's & 10’s complement.

24B81A0419

a) Derive POS form for F = Π(0, 2, 5, 6)& realize using NAND & NOR gates.

b) Subtract 485 - 378 using 9's & 10’s complement.

24B81A0420

b) Simplify F = Π(1, 2, 3, 4)& realize using NAND & NOR gates.

a) Subtract 700 - 199 using 9's & 10’s complement.

24B81A0421

a) Simplify F(W, X, Y, Z) = Σ(0, 2, 5, 7, 8, 10)& realize using NAND & NOR gates.

b) Subtract 10111010 - 01010101 using 1's & 2’s complement.

24B81A0422

b) Find minimal SOP for F = Σ(1, 3, 9, 11, 13)& realize using NAND & NOR gates.

a) Subtract 11100000 - 01100101 using 1's & 2’s complement.

24B81A0423

a) Use K-Map: F = Σ(0, 1, 2, 8, 9)& realize using NAND & NOR gates.

b) Subtract 00011101 - 11101100 using 1's & 2’s complement.

24B81A0424

b) Derive SOP for F = Σ(3, 5, 7, 15)& realize using NAND & NOR gates.

a) Subtract 10000001 - 10000001 using 1's & 2’s complement.

24B81A0425

a) Minimize F = Σ(0, 4, 8, 12)& realize using NAND & NOR gates.

b) Subtract 01101010 - 10111011 using 1's & 2’s complement.

24B81A0426

b) Use K-Map for F = Σ(2, 3, 6, 7)& realize using NAND & NOR gates.

a) Subtract 00111000 - 00011100 using 1's & 2’s complement.

24B81A0427

a) Simplify F = Σ(0, 1, 5, 7, 13)& realize using NAND & NOR gates.

b) Subtract 11111111 - 10101010 using 1's & 2’s complement.

24B81A0428

b) Derive SOP for F = Σ(4, 5, 6, 7)& realize using NAND & NOR gates.

a) Subtract 10000000 - 01111111 using 1's & 2’s complement.

24B81A0429

a) Use K-Map: F = Σ(1, 3, 5, 7, 9)& realize using NAND & NOR gates.

b) Subtract 01000000 - 10000000 using 1's & 2’s complement.

24B81A0430

b) Simplify F = Σ(6, 7, 14, 15)& realize using NAND & NOR gates.

a) Subtract 11110000 - 11100000 using 1's & 2’s complement.

24B81A0431

a) Simplify F = Π(2, 3, 6, 7, 10)& realize using NAND & NOR gates.

b) Subtract 10110110 - 01010110 using 1's & 2’s complement.

24B81A0432

b) Minimize F = Π(0, 1, 4, 5, 8)& realize using NAND & NOR gates.

a) Subtract 11100000 - 11111111 using 1's & 2’s complement.

24B81A0433

a) Find POS for F = Π(1, 3, 5, 7)& realize using NAND & NOR gates.

b) Subtract 10000001 - 00000001 using 1's & 2’s complement.

24B81A0434

b) Derive POS form: F = Π(9, 11, 13, 15)& realize using NAND & NOR gates.

a) Subtract 01100011 - 00110011 using 1's & 2’s complement.

24B81A0435

a) Simplify F = Π(0, 2, 4, 6, 8)& realize using NAND & NOR gates.

b) Subtract 10101010 - 11111111 using 1's & 2’s complement.

24B81A0436

b) Use K-Map for F = Π(5, 6, 7, 8)& realize using NAND & NOR gates.

a) Subtract 00010001 - 00000001 using 1's & 2’s complement.

24B81A0437

a) Derive POS form: F = Π(0, 1, 2, 3)& realize using NAND & NOR gates.

b) Subtract 01010101 - 10101010 using 1's & 2’s complement.

24B81A0438

b) Minimize F = Π(8, 10, 12, 14)& realize using NAND & NOR gates.

a) Subtract 00000000 - 11111111 using 1's & 2’s complement.

24B81A0439

a) Use K-Map: F = Π(3, 6, 9, 12)& realize using NAND & NOR gates.

b) Subtract 11111111 - 00000000 using 1's & 2’s complement.

24B81A0440

b) Simplify F = Π(2, 4, 6, 8, 10)& realize using NAND & NOR gates.

a) Subtract 01010101 - 01010101 using 1’s & 2's complement

24B81A0441

a) F = Σ(1, 2, 5), d = (0, 3)& realize using NAND & NOR gates.

b) Subtract 765 - 432 using 7's & 8’s complement.

24B81A0442

b) F = Σ(0, 3, 4), d = (1, 5)& realize using NAND & NOR gates.

a) Subtract 700 - 777 using 7's & 8’s complement.

24B81A0444

a) F = Σ(2, 6), d = (0, 1, 3)& realize using NAND & NOR gates.

b) Subtract 123 - 456 using 7's & 8’s complement.

24B81A0446

b) F = Σ(4, 5), d = (2, 7)& realize using NAND & NOR gates.

a) Subtract 741 - 132 using 7's & 8’s complement.

24B81A0447

a) F = Σ(1, 3, 6), d = (0, 2)& realize using NAND & NOR gates.

b) Subtract 354 - 123 using 7's & 8’s complement.

24B81A0448

b) F = Σ(1, 5), d = (3, 4, 6)& realize using NAND & NOR gates.

a) Subtract 255 - 644 using 7's & 8’s complement.

24B81A0449

a) F = Σ(0, 4), d = (1, 5, 7)& realize using NAND & NOR gates.

b) Subtract 123 - 123 using 7's & 8’s complement.

24B81A0450

b) F = Σ(3, 5), d = (0, 2, 6)& realize using NAND & NOR gates.

a) Subtract 644 - 123 using 7's & 8’s complement.

24B81A0451

a) F = Σ(1, 7), d = (3, 4, 6)& realize using NAND & NOR gates.

b) Subtract 777 - 321 using 7's & 8’s complement.

24B81A0452

b) F = Σ(2, 6), d = (0, 1, 5)& realize using NAND & NOR gates.

a) Subtract 123 - 765 using 7's & 8’s complement.

24B81A0453

a) F = Σ(1, 3, 5, 7), d = (0, 2)& realize using NAND & NOR gates.

b) Subtract 456 - 321 using 7's & 8’s complement.

24B81A0454

b) F = Σ(4, 6, 8, 10), d = (5, 9)& realize using NAND & NOR gates.

a) Subtract 700 - 345 using 7's & 8’s complement.

24B81A0455

a) F = Σ(3, 7, 11, 15), d = (1, 2)& realize using NAND & NOR gates.

b) Subtract 654 - 321 using 7's & 8’s complement.

24B81A0456

b) F = Σ(1, 2, 8, 9), d = (0, 3, 10)& realize using NAND & NOR gates.

a) Subtract 123 - 456 using 7's & 8’s complement.

24B81A0457

a) F = Σ(0, 1, 4, 5), d = (2, 6)& realize using NAND & NOR gates.

b) Subtract 400 - 200 using 7's & 8’s complement.

24B81A0458

b) F = Σ(5, 6, 7, 13), d = (4, 12)& realize using NAND & NOR gates.

a) Subtract 777 - 777 using 7's & 8’s complement.

24B81A0459

a) F = Σ(3, 6, 9), d = (2, 10, 11)& realize using NAND & NOR gates.

b) Subtract 765 - 111 using 7's & 8’s complement.

24B81A0460

b) F = Σ(2, 5, 8), d = (0, 4, 12)& realize using NAND & NOR gates.

a) Subtract 567 - 210 using 7's & 8’s complement.

24B81A0461

a) F = Σ(1, 3, 7), d = (6, 14)& realize using NAND & NOR gates.

b) Subtract 111 - 222 using 7's & 8’s complement.

24B81A0462

b) F = Σ(0, 6, 10), d = (4, 8, 12)& realize using NAND & NOR gates.

a) Subtract 321 - 123 using 7's & 8’s complement.

24B81A0463

a) F = Σ(1, 3, 5, 7), d = (0, 2)& realize using NAND & NOR gates.

b) Subtract A2F - 3BC using 15's & 16’s complement.

24B81A0464

b) Derive SOP for F = Σ(4, 5, 6, 7)& realize using NAND & NOR gates.

a) Subtract FFF - 789 using 15's & 16’s complement.

24B81A0465

a) Use K-Map: F = Σ(1, 3, 5, 7, 9)& realize using NAND & NOR gates.

b) Subtract 456 - AAA using 15's & 16’s complement.

24B81A0466

b) Use K-Map to simplify F = Π(0, 2, 3, 7)& realize using NAND & NOR gates.

a) Subtract 999 - 111 using 15's & 16’s complement.

LE-1

a) Simplify using K-Map: F = Π(1, 4, 6)& realize using NAND & NOR gates.

b) Subtract ABC - DEF using 15's & 16’s complement.

LE-2

b) Use K-Map to simplify F = Σ(1, 2, 4, 7)& realize using NAND & NOR gates.

a) Subtract 123 - 456 using 15's & 16’s complement.

LE-3

a) Derive minimal SOP form for F = Σ(3, 5, 7)& realize using NAND & NOR gates.

b) Subtract CBA - 999 using 15's & 16’s complement.

LE-4

b) Use K-Map for F = Σ(2, 3, 6, 7)& realize using NAND & NOR gates.

a) Subtract 555 - 555 using 15's & 16’s complement.

LE-5

a) Simplify F = Σ(0, 1, 5, 7, 13)& realize using NAND & NOR gates.

b) Subtract FFE - 001 using 15's & 16’s complement.

LE-6

b) Find POS for F = Π(3, 5, 7)& realize using NAND & NOR gates.

a) Subtract AAA - BBB using 15’s & 16'scomplement.

LE-7

a) Find sop for F = Π(3, 5,6 7)& realize using NAND & NOR gates.

b) Subtract A9A - D07 using 15’s & 16'scomplement.